74HC125D(BJ)

74HC125D,74HC126D CMOS Digital Integrated Circuits Silicon Monolithic 74HC125D,74HC126D74HC125D,74HC126D74HC125D,74HC126D74HC125D,74HC126D 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description Quad Bus Buffer, Non-Inverted 3-State Outputs 74HC125D: Quad Bus Buffer 74HC126D: Quad Bus Buffer 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74HC125D,74HC126D are high speed CMOS QUAD BUS BUFFERs fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The 74HC125D requires the 3-state control input G to be set high to place the output into the high impedance state, whereas the 74HC126D requires the control input to be set low to place the output into high impedance. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) High speed: t = 10 ns (typ.) at V = 6.0 V pd CC (2) Low power dissipation: I = 4.0 A (max) at T = 25 CC a (3) Balanced propagation delays: t t PLH PHL (4) Wide operating voltage range: V = 2.0 to 6.0 V CC(opr) 4. 4. 4. 4. PackagingPackagingPackagingPackaging SOIC14 Start of commercial production 2016-02 2016 Toshiba Corporation 2016-08-04 1 Rev.4.074HC125D,74HC126D 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 74HC125D 74HC126D 6. 6. 6. 6. MarkingMarkingMarkingMarking 74HC125D 74HC126D 7. 7. IEC Logic SymbolIEC Logic Symbol 7. 7. IEC Logic SymbolIEC Logic Symbol 74HC125D 74HC126D 2016 Toshiba Corporation 2016-08-04 2 Rev.4.0