M24LR64-RDW6/2

M24LR64-R 64 Kbit EEPROM with password protection & dual interface: 400 kHz IC serial bus & ISO 15693 RF protocol at 13.56 MHz Features 2 I C interface 2 Two-wire I C serial interface supports 400 kHz protocol Single supply voltage: SO8 (MN) 150 mils width 1.8 V to 5.5 V Byte and Page Write (up to 4 bytes) Random and Sequential Read modes Self-timed programming cycle Automatic address incrementing UFDFPN8 (MB) 2 3 mm Enhanced ESD/latch-up protection Contactless interface ISO 15693 and ISO 18000-3 mode 1 compliant 13.56 MHz 7k Hz carrier frequency To tag: 10% or 100% ASK modulation using 1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse TSSOP8 (DW) position coding From tag: load modulation using Manchester coding with 423 kHz and 484 kHz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with Fast commands Internal tuning capacitance: 27.5 pF 64-bit unique identifier (UID) Read Block & Write (32-bit Blocks) Memory Sawn wafer on UV tape 64 Kbit EEPROM organized into: 2 8192 bytes in I C mode Multiple password protection in RF mode 2048 blocks of 32 bits in RF mode 2 Single password protection in I C mode Write time 2 More than 40-year data retention I C: 5 ms (Max.) Package RF: 5.75 ms including the internal Verify time ECOPACK2 (RoHS compliant and Halogen-free) More than 1 Million write cycles August 2010 Doc ID 15170 Rev 11 1/128 www.st.com 1Contents M24LR64-R Contents 1 Description 12 2 Signal description 14 2.1 Serial Clock (SCL) 14 2.2 Serial Data (SDA) . 14 2.3 Chip Enable (E0, E1) 14 2.4 Antenna coil (AC0, AC1) . 14 2.5 V ground 14 SS 2.6 Supply voltage (V ) 15 CC 2.6.1 Operating supply voltage V CC . 15 2.6.2 Power-up conditions . 15 2.6.3 Device reset 15 2.6.4 Power-down conditions . 15 3 User memory organization . 18 4 System memory area . 23 4.1 M24LR64-R RF block security . 23 4.2 Example of the M24LR64-R security protection 25 4.3 I2C Write Lock bit area 26 4.4 System parameters . 26 2 4.5 M24LR64-R I C password security . 27 2 4.5.1 I C Present Password command description 27 2 4.5.2 I C Write Password command description 28 2 5I C device operation 30 5.1 Start condition . 30 5.2 Stop condition . 30 5.3 Acknowledge bit (ACK) . 30 5.4 Data Input . 30 5.5 Memory addressing . 31 5.6 Write operations 32 5.7 Byte Write . 32 2/128 Doc ID 15170 Rev 11