74AUP1G04DTR

74AUP1G04 Low power single inverter gate Features High speed: t = 4.3 ns (max.) at V = 2.3 V PD CC Power down protection on inputs and outputs Balanced propagation delays: t t PLH PHL Operating voltage range: DFN6L V (opr) = 1.2 to 3.6 V CC Low power dissipation: I = 1 A (max.) at T = 85 C CC A Latch-up performance exceeds 300 mA (JESD 78, Class II) ESD performance: SOT-665 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) Applications Description Mobile phones Personal digital assistants (PDAs) The 74AUP1G04 is a low voltage CMOS single inverter gate fabricated with sub-micron silicon 2 gate and double-layer metal wiring C MOS technology. It is ideal for 1.2 to 3.6 V operations and low power and low noise applications. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2kV ESD immunity and transient excess voltage. Table 1. Device summary Order code Package Packing 74AUPG04DTR DFN6L (1.2 x 1 mm) Tape and reel 74AUPG04GTR SOT-665 (1.6 x 1.6 mm) Tape and reel March 2008 Rev 1 1/18 www.st.com 18 Obsolete Product(s) - Obsolete Product(s)Pin settings 74AUP1G04 1 Pin settings 1.1 Pin connection Figure 1. Pin connection (top through view) 1 6 1 5 NC VCC NC VCC 2 5 2 A NC A 3 4 3 4 GND B GND B DFN6L SOT-665 CS00092 1.2 Pin description Table 2. Pin assignment DFN pin SOT pin Symbol Name and function number number 1 1 NC Not connected 2 2 A Data input 3 3 GND Ground (0V) 4 4 B Data output 5 - NC Not connected 65 V Positive supply voltage CC 2/18 Obsolete Product(s) - Obsolete Product(s)