S34ML04G100TFV000

S34ML01G1 S34ML02G1, S34ML04G1 1 Gb, 2 Gb, 4 Gb, 3 V SLC NAND Flash For Embedded Distinctive Characteristics Density NAND flash interface 1 Gb/ 2 Gb / 4 Gb Open NAND Flash Interface (ONFI) 1.0 compliant Address, Data and Commands multiplexed Architecture Input / Output Bus Width: 8-bits / 16-bits Supply voltage Page size: 3.3-V device: Vcc = 2.7 V ~ 3.6 V x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area Security x16 = 1056 (1024 + 32) words; 32 words is spare area One Time Programmable (OTP) area Block size: 64 Pages Hardware program/erase disabled during power transition x8 = 128 KB + 4 KB Additional features x16 = 64k + 2k words 2 Gb and 4 Gb parts support Multiplane Program and Erase Plane size: commands 1 Gb / 2 Gb: 1024 Blocks per Plane Supports Copy Back Program x8 = 128 MB + 4 MB 2 Gb and 4 Gb parts support Multiplane Copy Back Program x16 = 64M + 2M words Supports Read Cache 4 Gb: 2048 Blocks per Plane Electronic signature x8 = 256 MB+ 8 MB Manufacturer ID: 01h x16 = 128M + 4M words Device size: Operating temperature 1 Gb: 1 Plane per Device or 128 MB Industrial: -40 C to 85 C 2 Gb: 2 Planes per Device or 256 MB Automotive: -40 C to 105 C 4 Gb: 2 Planes per Device or 512 MB Performance Page Read / Program Reliability Random access: 25 s (Max) 100,000 Program / Erase cycles (Typ) (with 1 bit ECC per 528 bytes (x8) or 264 words (x16)) Sequential access: 25 ns (Min) 10 Year Data retention (Typ) Program time / Multiplane Program time: 200 s (Typ) For one plane structure (1-Gb density) Block Erase (S34ML01G1) Block zero is valid and will be valid for at least 1,000 program- Block Erase time: 2.0 ms (Typ) erase cycles with ECC Block Erase / Multiplane Erase (S34ML02G1, S34ML04G1) For two plane structures (2-Gb and 4-Gb densities) Block Erase time: 3.5 ms (Typ) Blocks zero and one are valid and will be valid for at least 1,000 program-erase cycles with ECC Package options Lead Free and Low Halogen 48-Pin TSOP 12 x 20 x 1.2 mm 63-Ball BGA 9 x 11 x 1 mm Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 002-00676 Rev. *T Revised Tuesday, May 16, 2017S34ML01G1 S34ML02G1, S34ML04G1 Contents Distinctive Characteristics .................................................. 1 5.7 Pin Capacitance............................................................ 37 5.8 Program / Erase Characteristics................................... 38 Performance.......................................................................... 1 6. Timing Diagrams......................................................... 38 1. General Description..................................................... 4 6.1 Command Latch Cycle.................................................. 38 1.1 Logic Diagram................................................................ 5 6.2 Address Latch Cycle..................................................... 39 1.2 Connection Diagram ...................................................... 6 6.3 Data Input Cycle Timing................................................ 39 1.3 Pin Description............................................................... 7 6.4 Data Output Cycle Timing (CLE=L, WE#=H, ALE=L, 1.4 Block Diagram................................................................ 8 WP#=H) ........................................................................ 40 1.5 Array Organization......................................................... 9 6.5 Data Output Cycle Timing (EDO Type, CLE=L, WE#=H, 1.6 Addressing................................................................... 10 ALE=L).......................................................................... 40 1.7 Mode Selection ............................................................ 13 6.6 Page Read Operation ................................................... 41 2. Bus Operation ............................................................ 13 6.7 Page Read Operation (Interrupted by CE#).................. 42 2.1 Command Input ........................................................... 13 6.8 Page Read Operation Timing with CE# Dont Care...... 43 2.2 Address Input............................................................... 13 6.9 Page Program Operation.............................................. 43 2.3 Data Input .................................................................... 14 6.10 Page Program Operation Timing with CE# Dont Care. 44 2.4 Data Output.................................................................. 14 6.11 Page Program Operation with Random Data Input ...... 44 2.5 Write Protect ................................................................ 14 6.12 Random Data Output In a Page ................................... 45 2.6 Standby........................................................................ 14 6.13 Multiplane Page Program Operation S34ML02G1 and S34ML04G1.................................................................. 45 3. Command Set............................................................. 15 6.14 Block Erase Operation.................................................. 46 3.1 Page Read................................................................... 16 6.15 Multiplane Block Erase S34ML02G1 and S34ML04G1 3.2 Page Program.............................................................. 16 47 3.3 Multiplane Program S34ML02G1 and S34ML04G1 17 6.16 Copy Back Read with Optional Data Readout.............. 48 3.4 Page Reprogram S34ML02G1 and S34ML04G1.... 18 6.17 Copy Back Program Operation With Random Data Input.. 3.5 Block Erase.................................................................. 19 48 3.6 Multiplane Block Erase S34ML02G1 and S34ML04G1 6.18 Multiplane Copy Back Program S34ML02G1 and 20 S34ML04G1.................................................................. 49 3.7 Copy Back Program..................................................... 20 6.19 Read Status Register Timing........................................ 50 3.8 EDC Operation S34ML02G1 and S34ML04G1....... 21 6.20 Read Status Enhanced Timing ..................................... 51 3.9 Read Status Register................................................... 23 6.21 Reset Operation Timing................................................ 51 3.10 Read Status Enhanced S34ML02G1 and S34ML04G1 6.22 Read Cache.................................................................. 52 23 6.23 Cache Program............................................................. 54 3.11 Read Status Register Field Definition.......................... 24 6.24 Multiplane Cache Program S34ML02G1 and 3.12 Reset............................................................................ 24 S34ML04G1.................................................................. 55 3.13 Read Cache................................................................. 24 6.25 Read ID Operation Timing ............................................ 57 3.14 Cache Program............................................................ 25 6.26 Read ID2 Operation Timing .......................................... 57 3.15 Multiplane Cache Program S34ML02G1 and 6.27 Read ONFI Signature Timing........................................ 58 S34ML04G1................................................................. 26 6.28 Read Parameter Page Timing ...................................... 58 3.16 Read ID........................................................................ 27 6.29 OTP Entry Timing ......................................................... 59 3.17 Read ID2...................................................................... 29 6.30 Power On and Data Protection Timing ......................... 59 3.18 Read ONFI Signature .................................................. 29 6.31 WP# Handling............................................................... 60 3.19 Read Parameter Page ................................................. 30 7. Physical Interface ....................................................... 61 3.20 One-Time Programmable (OTP) Entry ........................ 32 7.1 Physical Diagram.......................................................... 61 4. Signal Descriptions ................................................... 32 8. System Interface ......................................................... 63 4.1 Data Protection and Power On / Off Sequence ........... 32 4.2 Ready/Busy.................................................................. 33 9. Error Management ...................................................... 65 4.3 Write Protect Operation ............................................... 34 9.1 System Bad Block Replacement................................... 65 5. Electrical Characteristics.......................................... 35 9.2 Bad Block Management................................................ 66 5.1 Valid Blocks ................................................................. 35 10. Ordering Information.................................................. 67 5.2 Absolute Maximum Ratings ......................................... 35 11. Document History Page ............................................. 68 5.3 Recommended Operating Conditions.......................... 35 5.4 AC Test Conditions...................................................... 35 5.5 AC Characteristics ....................................................... 36 5.6 DC Characteristics....................................................... 37 Document Number: 002-00676 Rev. *T Page 2 of 73