Si4322 Universal ISM Band Si4322 FSK Receiver PIN ASSIGNMENTPIN ASSIGNMENTPIN ASSIGNMENT PIN ASSIGNMENTPIN ASSIGNMENT DESCRIPTION Silicon Labss Si4322 is a single chip, low power, multi-channel FSK receiver SDI 1 16 VDI designed for use in applications requiring FCC or ETSI conformance for 2 15 ARSSI SCK unlicensed use in the 868 and 915 MHz bands. Used in conjunction with 123456789 VDD nSEL 3 14 1 2345678 9 1 2345678 9 Silicon Labs FSK transmitters, the Si4322 is a flexible, low cost, and highly 1 2345678 9 SDO / FFIT 4 13 IN1 IA4322 123456789 integrated solution that does not require production alignments. All required nIRQ 5 12 IN2 RF functions are integrated. Only an external crystal and bypass filtering is DATA / nFFE 6 11 VSS needed for operation. DCLK / nFFS / CFIL 7 10 nRES CLK 8 9 XTL / REF The Si4322 has a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency hopping, bypassing multipath fading, and interference to achieve robust wireless links. The PLLs high resolution allows the usage of multiple channels in any of the bands. The This document refers to Si4322-IC Rev A0. baseband bandwidth (BW) is programmable to accommodate various See www.silabs.com/integration for any applicable deviation, data rate, and crystal tolerance requirements. The receiver employs errata. See back page for ordering information. the Zero-IF approach with I/Q demodulation, therefore no external components (except crystal and decoupling) are needed in a typical FEATURES application. The Si4322 is a complete analog RF and baseband receiver Fully integrated (low BOM, easy design-in) including a multi-band PLL synthesizer with an LNA, I/Q down converter No alignment required in production mixers, baseband filters and amplifiers, and I/Q demodulator. Fast settling, programmable, high-resolution PLL Fast frequency hopping capability The chip dramatically reduces the load on the microcontroller with integrated High bit rate (up to 115.2 kbps in digital mode and digital data processing: data filtering, clock recovery, data pattern recognition 256 kbps in analog mode) and integrated FIFO. The automatic frequency control (AFC) feature allows Direct differential antenna input using a low accuracy (low cost) crystal. To minimize the system cost, the chip Programmable baseband bandwidth (134 to 400 kHz) can provide a clock signal for the microcontroller, avoiding the need for two Analog and digital RSSI outputs crystals. Automatic frequency control (AFC) Data quality detection (DQD) Internal data filtering and clock recovery RX pattern recognition FUNCTIONAL BLOCK DIAGRAM SPI compatible serial control interface Clock and reset signals for microcontroller 48 bit RX data FIFO MIX I AMP OC 7 DCLK Standard 10 MHz crystal reference clk IN1 13 Wake-up timer I/Q Data Filt LNA Self cal. data Demod. CLK Rec 6 DATA IN2 12 Low battery detector MIX Q AMP OC 2.2 to 3.8 V supply voltage FIFO Low power consumption Low standby current (typ. 0.3 A) PLL & I/Q VCO RSSI COMP DQD AFC with cal. RF Parts BB Amp/Filt./Limiter Data processing units TYPICAL APPLICATIONS Remote control WTM CLK div Xosc LBD Controller Bias with cal. Home security and alarm Low Power parts Wireless keyboard/mouse and other PC peripherals Toy control 8 9 15 1 2 3 4 5 16 10 11 14 CLK XTL ARSSI SDI SCK nSEL SDO nIRQ VDI nRES VSS VDD Remote keyless entry Tire pressure monitoring Telemetry Personal/patient data logging Remote automatic meter reading Si4322-DS rev 1.1r 0308 www.silabs.comSi4322 DETAILED DESCRIPTION General Data Filtering and Clock Recovery The output data filtering can be completed by an external capacitor The Si4322 FSK receiver is the counterpart of the Silicon Labs FSK transmitter. It covers the unlicensed frequency bands at 868 or by using digital filtering according to the final application. and 915 MHz. The device facilitates compliance with FCC and ETSI Analog operation:Analog operation:Analog Analog operation:Analog operation:operation: The filter is an RC type low-pass filter and a requirements. Schmitt-trigger (St). The resistor (10k) and the St is integrated on The programmable PLL synthesizer determines the operating the chip. An (external) capacitor can be chosen according to the frequency, while preserving accuracy based on the on-chip crystal- actual bit-rate. In this mode the receiver can handle up to 256 kbps controlled reference oscillator. The PLLs high resolution allows for data rate. the use of multiple channels in any of the bands. Digital operation:Digital operation:Digital operation: The data fDigital operation:Digital operation: ilter is a digital realization of an analog RC filter followed by a comparator with hysteresis. In this mode there The receiver employs the Zero-IF approach with I/Q demodulation, is a clock recovery circuit (CR), which can provide synchronized clock allowing the use of a minimal number of external components in a to the data. With this clock the received data can fill the RX Data typical application. The Si4322 consists of a fully integrated multi- FIFO. The CR has three operation modes: fast, slow, and automatic. band PLL synthesizer, an LNA with switchable gain, I/Q down In slow mode, its noise immunity is very high, but it has slower settling converter mixers, baseband filters and amplifiers, and an I/Q time and requires more accurate data timing than in fast mode. In demodulator followed by a data filter. automatic mode the CR automatically changes between fast and LNA slow modes. The CR starts in fast mode, then automatically switches to slow mode after locking. The LNA has 250 Ohm input impedance, which works well with the recommended antennas. (See Application Notes available from (Only the data filter and the clock recovery use the bit-rate clock. www.silabs.com/integration.) Therefore, in analog mode, there is no need for setting the correct bit-rate.) If the RF input of the chip is connected to 50 Ohm devices, an external matching circuit is required to provide the correct matching Data Validity Blocks and to minimize the noise figure of the receiver. RSSIRSSIRSSI RSSIRSSI The LNA gain (and linearity) can be selected (0, 6, 12, 18 dB A digital RSSI output is provided to monitor the input signal level. It relative to the highest gain) according to RF signal strength. This is goes high if the received signal strength exceeds a given useful in an environment with strong interferers. preprogrammed level. An analog RSSI signal is also available. The Baseband Filters RSSI settling time depends on the filter capacitor used. The receiver bandwidth is selectable by programming the bandwidth (BW) of the baseband filters. This allows setting up the receiver according to the characteristics of the signal to be received. P1 An appropriate bandwidth can be selected to accommodate various FSK deviation, data rate, and crystal tolerance requirements. The RSSI P2 filter structure is a 7-th order Butterworth low-pass with 40 dB voltage P3 V suppression at 2*BW frequency. Offset cancellation is accomplished by using a high-pass filter with a cut-off frequency below 15 kHz. P4 Input Power dBm Voltage on ARRSI pin vs. Input RF power P1 -65 dBm 1300 mV P2 -65 dBm 1000 mV P3 -100 dBm 600 mV P4 -100 dBm 300 mV 2