Si4022 Universal ISM Band Si4022 FSK Transmitter PIN ASSIGNMENTPIN ASSIGNMENTPIN ASSIGNMENTPIN ASSIGNMENTPIN ASSIGNMENT DESCRIPTION Integrations Si4022 is a single chip, low power, multi-channel FSK SDI 1 16 FSK transmitter designed for use in applications requiring FCC or ETSI VDD SCK 2 15 conformance for unlicensed use in the bands at 868 and 915 MHz. Used in nSEL 3 14 VSS B conjunction with Integrations FSK receivers, it is a flexible, low cost, and SDO 4 13 RF02 highly integrated solution that does not require production alignments. All nIRQ 5 12 RF01 required RF functions are integrated. Only an external crystal and bypass CLK 6 11 VSS A filtering is needed for operation. VREFO 7 10 nRES VSS D 8 9 XTL / REF The transmitter has a completely integrated PLL for easy RF design, and its rapid settling time allows for fast frequency-hopping, bypassing multipath fading and interference to achieve robust wireless links. The PLLs high resolution allows the usage of multiple channels in any of the bands. In This document refers to Si4022-IC Rev A0. addition, highly stable and accurate FSK modulation is accomplished by See www.silabs.com/integration for any applicable direct closed-loop modulation with bit rates up to 115.2 kbps. errata. See back page for ordering information. The integrated power amplifier of the transmitter has an open-collector differential output and can directly drive a loop antenna with programmable FEATURES output level, no additional matching network is required. An automatic Fully integrated (low BOM, easy design-in) antenna tuning circuit is built in to avoid both costly trimming procedures No alignment required in production and de-tuning due to the hand effect. Fast settling, programmable, high-resolution PLL Fast frequency hopping capability For battery-operated applications the device supports various power saving Stable and accurate FSK modulation with modes with wake-up interrupt generation options based on a low battery programmable deviation voltage detector and a sleep timer. Several additional features ease system Programmable PLL loop bandwidth design. Power-on reset and clock signals are provided to the microcontroller. Direct loop antenna drive An on-chip baud rate generator and a data FIFO are available. The transmitter Automatic antenna tuning circuit is programmed and controlled via an SPI compatible interface. Programmable output power level SPI bus for interfacing with microcontroller Clock and reset signals for microcontroller 64 bit TX data FIFO FUNCTIONAL BLOCK DIAGRAM Integrated programmable crystal load capacitor Standard 10 MHz crystal reference Power-saving modes Multiple event handling options for wake-up 13 RF02 CRYSTAL REFERENCE XTL 9 SYNTHESIZER activation OSCILLATOR 12 RF01 Wake-up timer Low battery detection CLOCK FREQUENCY 2.2 to 3.8 V supply voltage LEVEL LOAD CAP Low power consumption 6 CLK Low standby current (typ. 0.3 A) 5 nIRQ LOW BAT LOW BATTERY 4 SDO TRESHOLD TYPICAL APPLICATIONS DETECT VDD 15 CONTROLLER 1 SDI Remote control VSS A 11 2 SCK TIMEOUT VDD B 14 Home security and alarm WAKE-UP 3 nSEL PERIOD TIMER Wireless keyboard/mouse and other PC peripherals VSS D 8 16 FSK Toy control VREFO 7 Remote keyless entry 10 Tire pressure monitoring nRES Telemetry Personal/patient data logging Remote automatic meter reading 1 IA4222-DS rev 1.1r 0308 www.silabs.com/integrationi Si4022 DETAILED FEATURE-LEVEL DESCRIPTION The Si4022 FSK transmitter is designed to cover the unlicensed Low Battery Voltage Detector frequency bands at 868, and 915 MHz. The device facilitates The low battery detector circuit monitors periodically (typ. 8 ms) compliance with FCC and ETSI requirements. the supply voltage and generates an interrupt if it falls below a programmable threshold level. PLL The programmable PLL synthesizer determines the operating Wake-Up Timer frequency, while preserving accuracy based on the on-chip The wake-up timer has very low current consumption (4 A max) crystal-controlled reference oscillator. The PLLs high resolution and can be programmed from 1 ms to several hours. allows the usage of multiple channels in any of the bands. The It calibrates itself to the crystal oscillator at every startup and FSK deviation is selectable (from 20 to 160 kHz with 20 kHz then at every 40 seconds with an accuracy of 0.5%. When the increments) to accommodate various bandwidth, data rate and crystal oscillator is switched off, the calibration circuit switches crystal tolerance requirements, and it is also highly accurate it back on only long enough for a quick calibration (a few due to the direct closed-loop modulation of the PLL. The milliseconds) to facilitate accurate wake-up timing. The periodic transmitted digital data can be sent asynchronously through autocalibration feature can be turned off. the FSK pin or over the control interface using the appropriate command. Event Handling The RF VCO in the PLL performs automatic calibration, which In order to minimize current consumption, the transmitter requires only a few microseconds. To ensure proper operation supports the sleep mode. Switching between the various modes in the programmed frequency band, the RF VCO is automatically is controlled by the appropriate bits in the Power Management calibrated upon activation of the synthesizer. Command (page 11). Si4022 generates an interrupt signal on several events (wake- RF Power Amplifier (PA) up timer timeout, low supply voltage detection, on-chip FIFO The power amplifier has an open-collector differential output almost empty). This signal can be used to wake up the and can directly drive a loop antenna with a programmable output microcontroller, effectively reducing the period the power level. An automatic antenna tuning circuit is built in to microcontroller has to be active. The cause of the interrupt can avoid costly trimming procedures and the so-called hand be read out from the receiver by the microcontroller through the effect. SDO pin. Crystal Oscillator and Microcontroller Clock Output Interface and Controller The chip has a single-pin crystal oscillator circuit, which provides An SPI compatible serial interface lets the user select the a 10 MHz reference signal for the PLL. To reduce external parts frequency band, center frequency of the synthesizer, and the and simplify design, the crystal load capacitor is internal and output power. Division ratio for the microcontroller clock, wake- programmable. Guidelines for selecting the appropriate crystal up timer period, and low supply voltage detector threshold are can be found later in this datasheet. The transmitter can supply also programmable. Any of these auxiliary functions can be the clock signal for the microcontroller, so accurate timing is disabled when not needed. All parameters are set to default after possible without the need for a second crystal. In normal power-on the programmed values are retained during sleep mode. operation it is divided from the reference 10 MHz. During sleep The interface supports the read-out of a status register, providing mode a low frequency (typical 32 kHz) output clock signal can detailed information about the status of the transmitter. be switched on. When the microcontroller turns the crystal oscillator off by clearing the appropriate bit using the Power Management Command, the chip provides a certain number (default is 128) of further clock pulses (clock tail) for the microcontroller to let it go to idle or sleep mode. 2