SLG7NT4129V

SLG7NT4129 SLG7NT4129 PCIE RTD3 General Description Pin Configuration Silego SLG7NT4129 is a low power and small form device. The SoC is housed in a 2.5mm x 2.5mm VDD DEVICE RESET 1 12 TDFN package which is optimal for using with small PWR CNTRL GPIO 2 11 PCIE WAKE devices. PLT RST 3 10 NC DEVICE WAKE WAKE GPIO 4 9 Features 5 8 NC RST CNTRL GPIO Low Power Consumption GND 6 7 NC Dynamic Supply Voltage RoHS Compliant / Halogen-Free Thermal Pad TDFN-12 Pb-Free TDFN-12 Package connected to GND TOP VIEW Output Summary 2 Outputs Open Drain 2 Outputs 3-State Block Diagram Silego Technology, Inc. Rev 1.01 SLG7NT4129 DS r101 Revised June 11, 2013 SLG7NT4129 GP r004 SLG7NT4129 PCIE RTD3 Pin Configuration Pin Pin Name Type Pin Description 1 VDD PWR Supply Voltage 2 PWR CNTRL GPIO Input Digital Input 3 PLT RST Input Digital Input 4 DEVICE WAKE Input/Output 3-State 5 RST CNTRL GPIO Input Digital Input 6 NC -- Keep floating or connect to GND 7 GND GND Ground 8 NC -- Keep floating or connect to GND 9 WAKE GPIO Output Open Drain 10 NC -- Keep floating or connect to GND 11 PCIE WAKE Input/Output 3-State 12 DEVICE RESET Output Open Drain Exposed Exposed Bottom Pad GND Ground Bottom Pad Ordering Information Part Number Package Type SLG7NT4129V V = TDFN-12 SLG7NT4129VTR VTR = TDFN-12 - Tape and Reel (3k units) SLG7NT4129 DS r101 Page 2