SX1211 Transceiver Ultra-Low Power Integrated UHF Transceiver WIRELESS & SENSING General Description Features The SX1211 is a low cost single-chip transceiver Low Rx power consumption: 3mA operating in the frequency ranges from 863-870, 902- Low Tx power consumption: 25 mA +10 dBm 928 MHz and 950-960 MHz. The SX1211 is optimized Good reception sensitivity: down to -107 dBm at for very low power consumption (3mA in receiver 25 kb/s in FSK, -113 dBm at 2kb/s in OOK mode). It incorporates a baseband modem with data Programmable RF output power: up to +12.5 dBm rates up to 200 kb/s. Data handling features include a in 8 steps sixty-four byte FIFO, packet handling, automatic CRC Packet handling feature with data whitening and generation and data whitening. Its highly integrated automatic CRC generation architecture allows for minimum external component Wide RSSI (Received Signal Strength Indicator) count whilst maintaining design flexibility. All major RF dynamic range, 70dB from Rx noise floor communication parameters are programmable and Bit rates up to 200 kb/s, NRZ coding most of them may be dynamically set. It complies with On-chip frequency synthesizer European (ETSI EN 300-220 V2.1.1) and North FSK and OOK modulation American (FCC part 15.247 and 15.249) regulatory Incoming sync word recognition standards. Built-in Bit-Synchronizer for incoming data and clock synchronization and recovery 5 x 5 mm TQFN package Ordering Information Optimized Circuit Configuration for Low-cost applications Table 1: Ordering Information Minimum Order Applications Part number Delivery Quantity / Multiple Wireless alarm and security systems SX1211I084TRT Tape & Reel 3000 pieces Wireless sensor networks SX1211I084T Tray 200 pieces Automated Meter Reading Home and building automation SX1211WS Wafer 1 wafer Industrial monitoring and control TQFN-32 package Operating range -40 +85C Remote Wireless Control T refers to Lead Free packaging This device is WEEE and RoHS compliant Application Circuit Schematic Rev 8 February 2013 Page 1 of 92 www.semtech.com SX1211 WIRELESS & SENSING Table of Contents 1. General Description ................................................................... 5 5.3.1. General Description ............................................................41 1.1. Simplified Block Diagram ........................................................ 5 5.3.2. Tx Processing .....................................................................41 1.2. Pin Diagram ............................................................................ 6 5.3.3. Rx Processing .....................................................................42 1.3. Pin Description ........................................................................ 7 5.3.4. Interrupt Signals Mapping ...................................................42 2. Electrical Characteristics ............................................................ 8 5.3.5. uC Connections ..................................................................43 2.1. ESD Notice.............................................................................. 8 5.3.6. Continuous Mode Example .................................................43 2.2. Absolute Maximum Ratings .................................................... 8 5.4. Buffered Mode .......................................................................44 2.3. Operating Range ..................................................................... 8 5.4.1. General Description ............................................................44 2.4. Chip Specification ................................................................... 8 5.4.2. Tx Processing .....................................................................44 2.4.1. Power Consumption ............................................................. 8 5.4.3. Rx Processing .....................................................................45 2.4.2. Frequency Synthesis ........................................................... 9 5.4.4. Interrupt Signals Mapping ...................................................46 2.4.3. Transmitter ........................................................................... 9 5.4.5. uC Connections ..................................................................47 2.4.4. Receiver ............................................................................. 10 5.4.6. Buffered Mode Example .....................................................47 2.4.5. Digital Specification ............................................................ 11 5.5. Packet Mode ..........................................................................49 3. Architecture Description ........................................................... 12 5.5.1. General Description ............................................................49 3.1. Power Supply Strategy.......................................................... 12 5.5.2. Packet Format .....................................................................49 3.2. Frequency Synthesis Description ......................................... 13 5.5.3. Tx Processing .....................................................................51 3.2.1. Reference Oscillator .......................................................... 13 5.5.4. Rx Processing .....................................................................51 3.2.2. CLKOUT Output ................................................................. 13 5.5.5. Packet Filtering ...................................................................52 3.2.3. PLL Architecture ................................................................ 14 5.5.6. DC-Free Data Mechanisms ................................................53 3.2.4. PLL Tradeoffs..................................................................... 14 5.5.7. Interrupt Signal Mapping .....................................................54 3.2.5. Voltage Controlled Oscillator ............................................. 15 5.5.8. uC Connections ..................................................................55 3.2.6. PLL Loop Filter ................................................................... 16 5.5.9. Packet Mode Example ........................................................56 3.2.7. PLL Lock Detection Indicator ............................................. 16 5.5.10. Additional Information .......................................................56 3.2.8. Frequency Calculation ....................................................... 16 6. Configuration and Status Registers ..........................................58 3.3. Transmitter Description ......................................................... 18 6.1. General Description ...............................................................58 3.3.1. Architecture Description ..................................................... 18 6.2. Main Configuration Register - MCParam ...............................58 3.3.2. Bit Rate Setting .................................................................. 19 6.3. Interrupt Configuration Parameters - IRQParam ...................60 3.3.3. Alternative Settings ............................................................ 19 6.4. Receiver Configuration parameters - RXParam ....................62 3.3.4. Fdev Setting in FSK Mode ................................................. 19 6.5. Sync Word Parameters - SYNCParam ..................................63 3.3.5. Fdev Setting in OOK Mode ................................................ 19 6.6. Transmitter Parameters - TXParam .......................................64 3.3.6. Interpolation Filter .............................................................. 20 6.7. Oscillator Parameters - OSCParam .......................................64 3.3.7. Power Amplifier .................................................................. 20 6.8. Packet Handling Parameters PKTParam ............................65 3.3.8. Common Input and Output Front-End ................................ 22 7. Application Information .............................................................66 3.4. Receiver Description ............................................................. 23 7.1. Crystal Resonator Specification .............................................66 3.4.1. Architecture ........................................................................ 23 7.2. Software for Frequency Calculation .......................................66 3.4.2. LNA and First Mixer ........................................................... 24 7.2.1. GUI ......................................................................................66 3.4.3. IF Gain and Second I/Q Mixer ........................................... 24 7.2.2dll for Automatic Production Bench ....................................66 3.4.4. Channel Filters ................................................................... 24 7.3. Switching Times and Procedures ..........................................66 3.4.5. Channel Filters Setting in FSK Mode ................................. 25 7.3.1. Optimized Receive Cycle ....................................................67 3.4.6. Channel Filters Setting in OOK Mode ................................ 26 7.3.2. Optimized Transmit Cycle ...................................................68 3.4.7. RSSI ................................................................................... 26 7.3.3. Transmitter Frequency Hop Optimized Cycle .....................69 3.4.8. Fdev Setting in Receive Mode ........................................... 28 7.3.4. Receiver Frequency Hop Optimized Cycle .........................70 3.4.9. FSK Demodulator .............................................................. 28 7.3.5. Rx Tx and Tx Rx Jump Cycles .......................................71 3.4.10. OOK Demodulator ........................................................... 28 7.4. Reset of the Chip ...................................................................72 3.4.11. Bit Synchronizer ............................................................... 31 7.4.1. POR ....................................................................................72 3.4.12. Alternative Settings .......................................................... 32 7.4.2. Manual Reset ......................................................................72 3.4.13. Data Output ...................................................................... 32 7.5. Reference Design ..................................................................73 4. Operating Modes...................................................................... 33 7.5.1. Application Schematic .........................................................73 4.1. Modes of Operation .............................................................. 33 7.5.2. PCB Layout .........................................................................73 4.2. Digital Pin Configuration vs. Chip Mode ............................... 33 7.5.3. Bill Of Material .....................................................................74 5. Data Processing ....................................................................... 34 7.5.4. SAW Filter Plot ....................................................................75 5.1. Overview ............................................................................... 34 7.5.5. Ordering Information for Tools ............................................75 5.1.1. Block Diagram .................................................................... 34 7.6. Reference Design Performance .............................................76 5.1.2. Data Operation Modes ....................................................... 34 7.6.1. Sensitivity Flatness .............................................................77 5.2. Control Block Description ...................................................... 35 7.6.2. Sensitivity vs. LO Drift .........................................................78 5.2.1. SPI Interface ...................................................................... 35 7.6.3. Sensitivity vs. Receiver BW ................................................79 5.2.2. FIFO ................................................................................... 38 7.6.4. Sensitivity Stability over Temperature and Voltage ............80 5.2.3. Sync Word Recognition ..................................................... 40 7.6.5. Sensitivity vs. Bit Rate ........................................................80 5.2.4. Packet Handler................................................................... 40 7.6.6. Adjacent Channel Rejection ................................................81 5.2.5. Control ................................................................................ 40 7.6.7. Output Power Flatness .......................................................82 5.3. Continuous Mode .................................................................. 41 7.6.8. Pout and IDD vs. PA Setting ...............................................83 Rev 8 February 2013 Page 2 of 92 www.semtech.com