Features Datasheet RX64M Group R01DS0173EJ0110 Renesas MCUs Rev.1.10 Oct 24, 2016 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 4-MB flash memory, 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, full-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface Features PLQP0176KB-A 24 24 mm, 0.5-mm pitch PLQP0144KA-A 20 20 mm, 0.5-mm pitch PLQP0100KB-A 14 14 mm, 0.5-mm pitch 32-bit RXv2 CPU core Max. operating frequency: 120 MHz Capable of 240 DMIPS in operation at 120 MHz Single precision 32-bit IEEE-754 floating point PTLG0177KA-A 8 8 mm, 0.5-mm pitch Two types of multiply-and-accumulation unit (between memories PTLG0145KA-A 7 7 mm, 0.5-mm pitch PTLG0100JA-A 7 7 mm, 0.65-mm pitch and between registers) 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) Divider (fastest instruction execution takes two CPU clock cycles) Fast interrupt PLBG0176GA-A 13 13mm, 0.8-mm pitch CISC Harvard architecture with 5-stage pipeline Variable-length instructions: Ultra-compact code Supports the memory protection unit (MPU) Various communications interfaces JTAG and FINE (one-line) debugging interfaces IEEE 1588-compliant Ethernet MAC (for 176- and 177-pin Low-power design and architecture products: 2 modules) Operation from a single 2.7- to 3.6-V supply PHY layer for host/function or OTG controller (1) with full-speed Low power consumption: A product that supports all peripheral USB 2.0 with battery charging transfer (only for 176- and 177-pin functions draws only 0.3mA/MHz (Typ.). products) RTC is capable of operation from a dedicated power supply. PHY layer (1) for host/function or OTG controller (1) with full- Four low-power modes speed USB 2.0 transfer CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up On-chip code flash memory, no wait states to 3 modules) Supports versions with up to 4 Mbytes of ROM SCIg and SCIh with multiple functionalities (up to 9) 120-MHz operation, 8.3-ns read cycle (no wait states) Choose from among asynchronous mode, clock-synchronous mode, User code is programmable by on-board or off-board programming. 2 smart-card interface mode, simplified SPI, simplified I C, and Programming/erasing as background operations (BGOs) extended serial mode. On-chip data flash memory SCIFA with 16-byte transmission and reception FIFOs (up to 4 64 Kbytes, reprogrammable up to 100,000 times interfaces) Programming/erasing as background operations (BGOs) 2 I C bus interface for transfer at up to 1 Mbps (up to 2 interfaces) Four-wire QSPI (1 interface) in addition to RSPIa (1 interface) On-chip SRAM Parallel data capture unit (PDC) for the CMOS camera interface (not 512 Kbytes of SRAM (no wait states) in 100-pin products) 32 Kbytes of RAM with ECC (one wait state, single-error correction SD host interface (optional: 1 interface) with a 1- or 4-bit SD bus for and double error detection) use with SD memory or SDIO 8 Kbytes of standby RAM (backup on deep software standby) External address space Data transfer Buses for full-speed data transfer (max. operating frequency of 60 DMAC: 8 channels MHz) DTC 8 CS areas EXDMAC: 2 channels 8-, 16-, or 32-bit bus space is selectable per area DMAC for the Ethernet controller: 3 channels for 176- and 177-pin Independent SDRAM area (128 Mbytes) products 2 channels for 100-, 144-, and 145-pin products Up to 29 extended-function timers Reset and supply management 16-bit TPUa, MTU3a, and GPTA: input capture, output compare, Power-on reset (POR) PWM waveform output Low voltage detection (LVD) with voltage settings 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 Clock functions channels) External crystal resonator or internal PLL for operation at 8 to 24 12-bit A/D converter MHz Two 12-bit units (8 channels for unit 0 21 channels for unit 1) Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 MHz Self diagnosis 120-kHz clock for the IWDTa Detection of analog input disconnection Real-time clock 12-bit D/A converter: 2 channels Adjustment functions (30 seconds, leap year, and error) On-chip operational amplifier output or direct input selectable Real-time clock counting and binary counting modes are selectable Temperature sensor for measuring temperature Time capture function within the chip (for capturing times in response to event-signal input) Encryption (optional) Independent watchdog timer AES (key lengths: 128, 192, and 256 bits) 120-kHz (1/2 LOCO frequency) clock operation DES (key lengths: 56 bits (DES) 3 56 bits (T-DES)) Useful functions for IEC60730 compliance SHA (SHA-1 (128), SHA-2 (224 or 256), HMAC (160, 224, or 256)) Oscillation-stoppage detection, frequency measurement, CRC, Up to 127 pins for general I/O ports IWDTa, self-diagnostic function for the A/D converter, etc. 5-V tolerance, open drain, input pull-up, switchable driving ability Register write protection function can protect values in important registers against overwriting. Operating temp. range 40 C to +85 C R01DS0173EJ0110 Rev.1.10 Page 1 of 228 Oct 24, 2016RX64M Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/9) Classification Module/Function Description CPU CPU Maximum operating frequency: 120 MHz 32-bit RX CPU (RXv2) Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory Code flash memory Capacity: 2 Mbytes, 2.5 Mbytes, 3 Mbytes, 4 Mbytes 120 MHz, no-wait access On-board programming: Four types Off-board programming (parallel programmer mode) The trusted memory (TM) function protects against the reading of programs from blocks 8 and 9. Data flash memory Capacity: 64 Kbytes Programming/erasing: 100,000 times RAM Capacity: 512 Kbytes 120 MHz, no-wait access SED (single error detection) Unique ID 12-byte length ID unique to the device RAM with ECC Capacity: 32 Kbytes 120 MHz, single wait access SEC-DED (single error correction/double error detection) Standby RAM Capacity: 8 Kbytes Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access Operating modes Operating modes by the mode-setting pins at the time of release from the reset state Single-chip mode Boot mode (for the SCI interface) Boot mode (for the USB interface) User boot mode Selection of operating mode by register setting Single-chip mode, user boot mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Endian selectable R01DS0173EJ0110 Rev.1.10 Page 2 of 228 Oct 24, 2016