KMB-001CEVALZ

DATASHEET KAD2708C FN6812 Rev 1.00 8-Bit, 275/210/170/105MSPS A/D Converter April 14, 2011 The KAD2708C is the industrys lowest power, 8-bit, Features 275MSPS, high performance Analog-to-Digital converter. It On-Chip Reference is designed with Intersils proprietary FemtoCharge technology on a standard CMOS process. The KAD2708C Internal Track and Hold offers high dynamic performance (49.2dBFS SNR 1.5V Differential Input Voltage P-P f = 138MHz) while consuming less than 265mW. Features IN 600MHz Analog Input Bandwidth include an over-range indicator and a selectable divide-by-2 input clock divider. The KAD2708C is one member of a Twos Complement or Binary Output pin-compatible family offering 8 and 10-bit ADCs with Over-Range Indicator sample rates from 105MSPS to 350MSPS and LVCMOS or LVDS-compatible outputs (Table 1). This family of products Selectable 2 Clock Input is available in 68-pin RoHS-compliant QFN packages with LVCMOS Outputs exposed paddle. Performance is specified over the full industrial temperature range (-40C to +85C). Applications High-Performance Data Acquisition Portable Oscilloscope CLK P CLKOUT Medical Imaging Clock Generation CLK N Cable Head Ends Power-Amplifier Linearization D7 D0 Radar and Satellite Antenna Array Processing INP 8-bit 8 LVCMOS OR S/H 275MSPS Drivers Broadband Communications INN ADC VREF Point-to-Point Microwave Systems 1.21 V 2SC + VREFSEL Communications Test Equipment VCM Key Specifications SNR of 49.2dBFS at f = 275MSPS, f = 138MHz S IN SFDR of 66.6dBc at f = 275MSPS, f = 138MHz S IN Ordering Information Power Consumption 265mW at f = 275MSPS S SPEED TEMP. PART NUMBER (MSPS) RANGE (C) PACKAGE PKG. DWG. Pin-Compatible Family KAD2708C-27Q68 275 -40 to +85 68 Ld QFN L68.10x10B TABLE 1. PIN-COMPATIBLE PRODUCTS KAD2708C-21Q68 210 -40 to +85 68 Ld QFN L68.10x10B RESOLUTION, SPEED LVDS OUTPUTS LVCMOS OUTPUTS KAD2708C-17Q68 170 -40 to +85 68 Ld QFN L68.10x10B 8 Bits 350MSPS KAD2708L-35 KAD2708C-10Q68 105 -40 to +85 68 Ld QFN L68.10x10B 10 Bits 275MSPS KAD2710L-27 KAD2710C-27 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb- 8 Bits 275MSPS KAD2708L-27 KAD2708C-27 free material sets, molding compounds/die attach materials, and 100% 10 Bits 210MSPS KAD2710L-21 KAD2710C-21 matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering 8 Bits 210MSPS KAD2708L-21 KAD2708C-21 operations). Intersil Pb-free products are MSL classified at Pb-free 10 Bits 170MSPS KAD2710L-17 KAD2710C-17 peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 8 Bits 170MSPS KAD2708L-17 KAD2708C-17 2. For Moisture Sensitivity Level (MSL), please see device information 10 Bits 105MSPS KAD2710L-10 KAD2710C-10 page for KAD2708C-10, KAD2708C-17, KAD2708C-21 and KAD2708C-27. For more information on MSL please see techbrief 8 Bits 105MSPS KAD2708L-10 KAD2708C-10 TB363. FN6812 Rev 1.00 Page 1 of 17 April 14, 2011 NOT RECOMMENDED FOR NEW DESIGNS R M DE EPL CEM NT NO ECO MEN D R A E contact our Technical Support Center at /t 1-888-INTERSIL or www.intersil.com sc AVDD2 AVSS AVDD3 CLKDIV OVDD OVSSKAD2708C Table of Contents Absolute Maximum Ratings ........................................ 3 Thermal Information ..................................................... 3 Electrical Specifications .............................................. 3 Digital Specifications ................................................... 4 Timing Diagram ............................................................ 6 Timing Specifications .................................................. 6 ESD ................................................................................ 6 Pin Descriptions ........................................................... 7 Pin Configuration ......................................................... 8 Typical Performance Curves ....................................... 9 Functional Description ................................................ 12 Reset ........................................................................12 Voltage Reference ....................................................12 Analog Input .............................................................12 Clock Input ................................................................13 Jitter ..........................................................................13 Digital Outputs ..........................................................14 Equivalent Circuits ....................................................... 14 Layout Considerations ................................................ 15 Split Ground and Power Planes ...............................15 Clock Input Considerations .......................................15 Bypass and Filtering .................................................15 LVCMOS Outputs .....................................................15 Unused Inputs ..........................................................15 Definitions ..................................................................... 15 Package Outline Drawing ............................................ 16 FN6812 Rev 1.00 Page 2 of 17 April 14, 2011