DATASHEET KAD5512P-50 FN6805 Rev 4.00 12-Bit, 500MSPS A/D Converter May 31, 2016 The KAD5512P-50 is a low-power, high performance, 12-bit, Features 500MSPS analog-to-digital converter designed with Intersils Programmable gain, offset and skew control proprietary FemtoCharge technology on a standard CMOS process. The KAD5512P-50 is part of a pin-compatible 1.3GHz analog input bandwidth portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging 60fs clock jitter from 125MSPS to 500MSPS. Over-range indicator The device utilizes two time-interleaved 12-bit, 250MSPS A/D Selectable clock divider: 1 or 2 cores to achieve the ultimate sample rate of 500MSPS. A single 500MHz conversion clock is presented to the converter, Clock phase selection and all interleave clocking is managed internally. Nap and sleep modes A Serial Peripheral Interface (SPI) port allows for extensive Twos complement, gray code or binary data format configurability, as well as fine control of matching DDR LVDS-compatible or LVCMOS outputs characteristics (gain, offset, skew) between the two converter cores. These adjustments allow the user to minimize spurs Programmable built-in test patterns associated with the interleaving process. Single-supply 1.8V operation Digital output data is presented in selectable LVDS or CMOS Pb-free (RoHS compliant) formats. The KAD5512P-50 is available in a 72 Ld QFN package with an exposed paddle. Performance is specified Applications across the full industrial temperature range (-40C to +85C). Radar and satellite antenna array processing Broadband communications Key Specifications High-performance data acquisition SNR = 65.9dBFS for f = 105MHz (-1dBFS) IN SFDR = 82.0dBc for f = 105MHz (-1dBFS) IN Total power consumption = 432mW CLKP CLOCK GENERATION CLKOUTP AND CLKN INTERLEAVE CONTROL CLKOUTN 12-BIT D 11:0 P SHA 250 MSPS ADC D 11:0 N VREF ORP VINP DIGITAL ORN ERROR CORRECTION VINN OUTFMT OUTMODE 12-BIT VCM SHA 250 MSPS ADC VREF + 1.25V SPI CONTROL FIGURE 1. BLOCK DIAGRAM FN6805 Rev 4.00 Page 1 of 29 May 31, 2016 NAPSLP AGND AVDD CLKDIV RESETN CSB SCLK SDIO SDO OGND OVDDKAD5512P-50 Table of Contents Ordering Information 3 Absolute Maximum Ratings . 4 Thermal Information . 4 Electrical Specifications . 4 Digital Specifications 6 Timing Diagrams 6 Switching Specifications . 7 Pin Descriptions . 8 Pin Configuration . 10 Typical Performance Curves . 11 Theory of Operation . 14 Functional Description . 14 Power-On Calibration . 14 User Initiated Reset 15 Analog Input 15 Clock Input . 16 Jitter . 17 Voltage Reference . 17 Digital Outputs 17 Over-Range Indicator . 17 Power Dissipation . 17 Nap/Sleep 17 Data Format 18 Serial Peripheral Interface 20 SPI Physical Interface 20 SPI Configuration 21 Device Information 21 Indexed Device Configuration/Control 21 Global Device Configuration/Control . 22 Device Test . 23 SPI Memory Map 24 Equivalent Circuits . 25 ADC Evaluation Platform 26 Layout Considerations 26 Split Ground and Power Planes 26 Clock Input Considerations 26 Exposed Paddle . 26 Bypass and Filtering . 26 LVDS Outputs . 26 LVCMOS Outputs 26 Unused Inputs 27 Definitions 27 Revision History 27 About Intersil 28 Package Outline Drawing 29 FN6805 Rev 4.00 Page 2 of 29 May 31, 2016