89HPES16T4AG2 16-Lane 4-Port Data Sheet Gen2 PCI Express Switch Flexible Architecture with Numerous Configuration Options Device Overview Automatic per port link width negotiation to x8, x4, x2 or x1 The 89HPES16T4AG2 is a member of IDTs PRECISE family of PCI Express switching solutions. The PES16T4AG2 is a 16-lane, 4- Automatic lane reversal on all ports port Gen2 peripheral chip that performs PCI Express Base switching Automatic polarity inversion with a feature set optimized for high performance applications such as Ability to load device configuration from serial EEPROM servers, storage, and communications/networking. It provides connec- Legacy Support tivity and switching functions between a PCI Express upstream port and PCI compatible INTx emulation up to three downstream ports and supports switching between down- Bus locking stream ports. Highly Integrated Solution Incorporates on-chip internal memory for packet buffering and Features High Performance PCI Express Switch queueing Integrates sixteen 5 Gbps embedded SerDes with 8b/10b Sixteen 5 Gbps Gen2 PCI Express lanes encoder/decoder (no separate transceivers needed) Four switch ports Receive equalization (RxEQ) One x8 or x4 upstream port Reliability, Availability, and Serviceability (RAS) Features Up to three x4 downstream ports Internal end-to-end parity protection on all TLPs ensures data Low latency cut-through switch architecture integrity even in systems that do not implement end-to-end Support for Max Payload Size up to 2048 bytes CRC (ECRC) One virtual channel Supports ECRC and Advanced Error Reporting Eight traffic classes All internal data and control RAMs are SECDED ECC PCI Express Base Specification Revision 2.0 compliant protected Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O Compatible with Hot-Plug I/O expanders used on PC mother- boards Supports Hot-Swap Block Diagram 4-Port Switch Core / 16 PCI Express Lanes Port Frame Buffer Route Table Scheduler Arbitration Transaction Layer Transaction Layer Transaction Layer Transaction Layer Data Link Layer Data Link Layer Data Link Layer Data Link Layer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Multiplexer / Demultiplexer Phy Phy Phy Phy Logical Logical Logical Logical Layer Layer Layer Layer SerDes SerDes SerDes SerDes (Port 0) (Port 1) (Port 2) (Port 3) Figure 1 Internal Block Diagram IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 32 June 2, 2015 DSC 6928IDT 89HPES16T4AG2 Data Sheet Power Management Utilizes advanced low-power design techniques to achieve low typical power consumption Processor Processor Support PCI Express Power Management Interface specifica- tion (PCI-PM 2.0) Unused SerDes are disabled. Memory North Memory Memory Memory Supports Advanced Configuration and Power Interface Spec- Bridge ification, Revision 2.0 (ACPI) supporting active link state x8/x4 Testability and Debug Features Built in Pseudo-Random Bit Stream (PRBS) generator PES16T4AG2 Numerous SerDes test modes Ability to read and write any internal register via the SMBus x4 x4 x4 Ability to bypass link training and force any link into any mode Provides statistics and performance counters I/O I/O I/O I/O PCI Express Seven General Purpose Input/Output Pins 10GbE 10GbE SATA SATA Slot Each pin may be individually configured as an input or output Each pin may be individually configured as an interrupt input Figure 2 I/O Expansion Application Some pins have selectable alternate functions Packaged in a 19mm x 19mm, 324-ball Flip Chip BGA with SMBus Interface 1mm ball spacing The PES16T4AG2 contains two SMBus interfaces. The slave inter- face provides full access to the configuration registers in the Product Description PES16T4AG2, allowing every configuration register in the device to be Utilizing standard PCI Express interconnect, the PES16T4AG2 read or written by an external agent. The master interface allows the provides the most efficient fan-out solution for applications requiring high default configuration register values of the PES16T4AG2 to be over- throughput, low latency, and simple board layout with a minimum ridden following a reset with values programmed in an external serial number of board layers. It provides 16 GBps (128 Gbps) of aggregated, EEPROM. The master interface is also used by an external Hot-Plug I/O full-duplex switching capacity through 16 integrated serial lanes, using expander. proven and robust IDT technology. Each lane provides 5 Gbps of band- Two pins make up each of the two SMBus interfaces. These pins width in both directions and is fully compliant with PCI Express Base consist of an SMBus clock pin and an SMBus data pin. The Master Specification, Revision 2.0. SMBus address is hardwired to 0x50, and the slave SMBus address is The PES16T4AG2 is based on a flexible and efficient layered archi- hardwired to 0x77. tecture. The PCI Express layer consists of SerDes, Physical, Data Link As shown in Figure 3, the master and slave SMBuses may be used and Transaction layers in compliance with PCI Express Base specifica- in a unified or split configuration. In the unified configuration, shown in tion Revision 2.0. The PES16T4AG2 can operate either as a store and Figure 3(a), the master and slave SMBuses are tied together and the forward or cut-through switch and is designed to switch memory and I/O PES16T4AG2 acts both as a SMBus master as well as a SMBus slave transactions. It supports eight Traffic Classes (TCs) and one Virtual on this bus. This requires that the SMBus master or processor that has Channel (VC) with sophisticated resource management to enable effi- access to PES16T4AG2 registers supports SMBus arbitration. In some cient switching and I/O connectivity for servers, storage, and embedded systems, this SMBus master interface may be implemented using processors with limited connectivity. general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To support these systems, the PES16T4AG2 may be configured to operate in a split configuration as shown in Figure 3(b). In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required. The PES16T4AG2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of the serial EEPROM. 2 of 32 June 2, 2015