89HPES32NT8AG2
32-Lane 8-Port PCIe Gen2
Datasheet
System Interconnect Switch
All BARs support 32/64-bit base and limit address translation
Device Overview
Two BARs (BAR2 and BAR4) support look-up table based
The 89HPES32NT8AG2 is a member of the IDT family of PCI
address translation
Express switching solutions. The PES32NT8AG2 is a 32-lane, 8-port
32 inbound and outbound doorbell registers
system interconnect switch optimized for PCI Express Gen2 packet
4 inbound and outbound message registers
switching in high-performance applications, supporting multiple simulta-
Supports up to 64 masters
neous peer-to-peer traffic flows. Target applications include multi-host or
Unlimited number of outstanding transactions
intelligent I/O based systems where inter-domain communication is
Multicast
required, such as servers, storage, communications, and embedded
systems.
Compliant with the PCI-SIG multicast
Supports 64 multicast groups
Features
Supports multicast across non-transparent port
High Performance Non-Blocking Switch Architecture
Multicast overlay mechanism support
32-lane, 8-port PCIe switch with flexible port configuration
ECRC regeneration support
Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s
Integrated Direct Memory Access (DMA) Controllers
Gen1 operation
Supports up to 2 DMA upstream ports, each with 2 DMA chan-
Delivers up to 32 GBps (256 Gbps) of switching capacity
nels
Supports 128 Bytes to 2 KB maximum payload size
Supports 32-bit and 64-bit memory-to-memory transfers
Low latency cut-through architecture
Fly-by translation provides reduced latency and increased
Supports one virtual channel and eight traffic classes
performance over buffered approach
Port Configurability
Supports arbitrary source and destination address alignment
Eight x4 switch ports
Supports intra- as well as inter-partition data transfers using
Adjacent x4 ports can be merged to achieve x8 port widths
the non-transparent endpoint
Automatic per port link width negotiation
Supports DMA transfers to multicast groups
(x8 x4 x2 x1)
Linked list descriptor-based operation
Crosslink support
Flexible addressing modes
Automatic lane reversal
Linear addressing
Per lane SerDes configuration
Constant addressing
De-emphasis
Quality of Service (QoS)
Receive equalization
Port arbitration
Drive strength
Round robin
Innovative Switch Partitioning Feature
Request metering
Supports up to 8 fully independent switch partitions
IDT proprietary feature that balances bandwidth among
Logically independent switches in the same device
switch ports for maximum system throughput
Configurable downstream port device numbering
High performance switch core architecture
Supports dynamic reconfiguration of switch partitions
Combined Input Output Queued (CIOQ) switch architecture
Dynamic port reconfiguration downstream, upstream, with large buffers
non-transparent bridge
Clocking
Dynamic migration of ports between partitions
Supports 100 MHz and 125 MHz reference clock frequencies
Movable upstream port within and between switch partitions
Flexible port clocking modes
Non-Transparent Bridging (NTB) Support
Common clock
Supports up to 8 NT endpoints per switch, each endpoint can
Non-common clock
communicate with other switch partitions or external PCIe
Local port clock with SSC (spread spectrum setting) and port
domains or CPUs
reference clock input
6 BARs per NT Endpoint
Bar address translation
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
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2013 Integrated Device Technology, IncIDT 89HPES32NT8AG2 Datasheet
Hot-Plug and Hot Swap Standards and Compatibility
Hot-plug controller on all ports PCI Express Base Specification 2.1 compliant
Hot-plug supported on all downstream switch ports Implements the following optional PCI Express features
2
All ports support hot-plug using low-cost external I C I/O Advanced Error Reporting (AER) on all ports
expanders
End-to-End CRC (ECRC)
Configurable presence-detect supports card and cable appli-
Access Control Services (ACS)
cations
Device Serial Number Enhanced Capability
GPE output pin for hot-plug event notification
Sub-System ID and Sub-System Vendor ID Capability
Enables SCI/SMI generation for legacy operating system
Internal Error Reporting
support
Multicast
Hot-swap capable I/O
VGA and ISA enable
Power Management
L0s and L1 ASPM
Supports D0, D3hot and D3 power management states
ARI
Active State Power Management (ASPM)
Power Supplies
Supports L0, L0s, L1, L2/L3 Ready, and L3 link states
Requires three power supply voltages (1.0V, 2.5V, and 3.3V)
Configurable L0s and L1 entry timers allow performance/
Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with
power-savings tuning
1mm ball spacing
SerDes power savings
Supports low swing / half-swing SerDes operation
Product Description
SerDes associated with unused ports are turned off
With Non-Transparent Bridging functionality and innovative Switch
SerDes associated with unused lanes are placed in a low
Partitioning feature, the PES32NT8AG2 allows true multi-host or multi-
power state
processor communications in a single device. Integrated DMA control-
Reliability, Availability, and Serviceability (RAS)
lers enable high-performance system design by off-loading data transfer
ECRC support
operations across memories from the processors. Each lane is capable
AER on all ports
of 5 GT/s link speed in both directions and is fully compliant with PCI
SECDED ECC protection on all internal RAMs Express Base Specification 2.1.
End-to-end data path parity protection
A non-transparent bridge (NTB) is required when two PCI Express
Checksum Serial EEPROM content protected
domains need to communicate to each other. The main function of the
Ability to generate an interrupt (INTx or MSI) on link up/down
NTB block is to initialize and translate addresses and device IDs to
transitions
allow data exchange across PCI Express domains. The major function-
Initialization / Configuration
alities of the NTB block are summarized in Table 1.
Supports Root (BIOS, OS, or driver), Serial EEPROM, or
SMBus switch initialization
Common switch configurations are supported with pin strap-
ping (no external components)
Supports in-system Serial EEPROM initialization/program-
ming
On-Die Temperature Sensor
Range of 0 to 127.5 degrees Celsius
Three programmable temperature thresholds with over and
under temperature threshold alarms
Automatic recording of maximum high or minimum low
temperature
9 General Purpose I/O
Test and Debug
Ability to inject AER errors simplifies in system error handling
software validation
On-chip link activity and status outputs available for several
ports
Per port link activity and status outputs available using
2
external I C I/O expander for all remaining ports
Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
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