Low Skew, 1-to-2, Differential-to-2.5V, 3.3V 85311 LVPECL/ ECL Fanout Buffer Datasheet General Description Features The 85311 is a low skew, high performance 1-to-2 Differential-to- Two differential 2.5V/3.3V LVPECL / ECL outputs 2.5V/3.3V ECL/LVPECL Fanout Buffer and a member of the high One CLK, nCLK input pair performance clock solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels. The 85311 is CLK, nCLK pair can accept the following differential input levels: characterized to operate from either a 2.5V or a 3.3V power supply. LVDS, LVPECL, LVHSTL, SSTL, HCSL Guaranteed output and part-to-part skew characteristics make the 85311 ideal for those clock distribution applications demanding well Maximum output frequency: 1GHz defined performance and repeatability. Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input Output skew: 15ps (maximum) Part-to-part skew: 100ps (maximum) Propagation delay: 1.4ns (maximum) Additive phase jitter, RMS: 0.14ps (typical), 3.3V LVPECL mode operating voltage supply range: V = 2.375V to 3.465V, V = 0V CC EE ECL mode operating voltage supply range: = 0V, V = -2.375V to -3.465V V CC EE 0C to 70C ambient operating temperature Available in lead-free (RoHS 6) package Block Diagram Pin Assignment Q0 Q0 1 8 VCC nQ0 Pulldown CLK nQ0 2 7 CLK Pullup nCLK Q1 nCLK 3 6 Q1 nQ1 4 5 VEE nQ1 85311 8-Lead SOIC 3.90mm x 4.903mm x 1.37mm package body M Package Top View 2016 Integrated Device Technology, Inc. 1 Revision E, February 18, 201685311 Datasheet Pin Descriptions and Pin Characteristic Tables Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5V Power Negative supply pin. EE 6 nCLK Input Pullup Inverting differential clock input. 7 CLK Input Pulldown Non-inverting differential clock input. Power Positive supply pin. 8V CC NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units Input Capacitance 4pF C IN R Input Pullup Resistor 51 k PULLUP R Input Pulldown Resistor 51 k PULLDOWN 2016 Integrated Device Technology, Inc. 2 Revision E, February 18, 2016