HIGH-SPEED 3.3V 64K x18/x16 IDT70V9389/289L SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features: True Dual-Ported memory cells which allow simultaneous Full synchronous operation on both ports access of the same memory location 3.5ns setup to clock and 0ns hold on all control, data, and High-speed clock to data access address inputs Commercial: 6/7.5/9/12ns (max.) Data input, address, and control registers Industrial: 9ns (max.) Fast 6.5ns clock to data out in the Pipelined output mode Low-power operation Self-timed write allows fast cycle time IDT70V9389/289L 10ns cycle time, 100MHz operation in Pipelined output mode Active: 500mW (typ.) Separate upper-byte and lower-byte controls for Standby: 1.5mW (typ.) multiplexed bus and bus matching compatibility Flow-Through or Pipelined output mode on either port via LVTTL- compatible, single 3.3V (0.3V) power supply the FT/PIPE pins Industrial temperature range (40C to +85C) is Counter enable and reset features available for selected speeds Dual chip enables allow for depth expansion without Available in a 128-pin Thin Quad Flatpack (TQFP) and additional logic 100-pin Thin Quad Flatpack (TQFP) Green parts available, see ordering information Functional Block Diagram R/WL R/WR UBL UBR CE0L CE0R 1 1 CE1L CE1R 0 0 0/1 0/1 LBL LBR OEL OER 1b 0b 1a 0a 0a 1a 0b 1b FT/PIPEL 0/1 ba 0/1 FT/PIPER ab (2) (1) I/O9L-I/O17L I/O9R-I/O17R I/O I/O Control Control (1) (1) I/O0L-I/O8L I/O0R-I/O8R A15L A15R Counter/ Counter/ A0L MEMORY A0R Address Address CLKL CLKR ARRAY Reg. ADSL Reg. ADSR CNTENL CNTENR CNTRSTL CNTRSTR 4856 drw 01 NOTE: 1. I/O0X - I/O7X for IDT70V9289. 2. I/O8X - I/O15X for IDT70V9289. JANUARY 2009 1 2009 Integrated Device Technology, Inc. DSC-4856/6IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM Industrial & Commercial Temperature Ranges Description: The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit With an input data register, the IDT70V9389/289 has been optimized synchronous Dual-Port RAM. The memory array utilizes Dual-Port for applications having unidirectional or bidirectional data flow in bursts. An memory cells to allow simultaneous access of any address from both ports. automatic power down feature, controlled by CE0 and CE1, permits the Registers on control, data, and address inputs provide minimal setup and on-chip circuitry of each port to enter a very low standby power mode. hold times. The timing latitude provided by this approach allows systems Fabricated using IDTs CMOS high-performance technology, these to be designed with very short cycle times. devices typically operate on only 500mW of power. (1,2,3) Pin Configuration 03/28/03 1 102 I/O12R NC I/O11R NC 2 101 VSS NC 3 100 NC 99 NC 4 A9R I/O10R 5 98 A8R 97 I/O9R 6 A7R I/O8R 96 7 A6R 8 95 I/O7R VDD A5R 9 94 I/O6R A4R 10 93 I/O5R A3R 92 11 A2R 12 91 I/O4R VSS 90 A1R 13 89 I/O3R A0R 14 88 VDD 15 NC 16 87 I/O2R CNTENR CLKR 86 I/O1R 17 70V9389PRF 85 I/O0R ADSR 18 (4) PK-128-1 VSS 84 VSS 19 VDD VDD 20 83 82 I/O0L ADSL 21 128-Pin TQFP CLKL 81 I/O1L 22 (5) VSS 80 CNTENL 23 Top View 79 I/O2L NC 24 78 I/O3L A0L 25 77 VSS 26 A1L A2L 76 I/O4L 27 75 I/O5L A3L 28 74 I/O6L A4L 29 73 I/O7L A5L 30 72 VDD A6L 31 71 I/O8L A7L 32 70 I/O9L A8L 33 A9L 69 I/O10L 34 68 NC NC 35 VDD 67 NC 36 66 I/O11L NC 37 65 I/O12L 38 NC 4856 drw 02 NOTES: 1. All VDD pins must be connected to power supply. SS pins must be connected to ground. 2. All V 3. Package body is approximately 14mm x 20mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. 6.42 2 128 A 10R A10L 39 127 A 11R A11L 40 126 A 12R A12L 41 125 A 13R A13L 42 124 A 14R A14L 43 123 A 15R A15L 44 122 NC NC 45 121 NC NC 46 120 LB R LBL 47 119 UB R UBL 48 CE 0R 118 CE 0L 49 117 CE 1R CE 1L 50 CNTRSTR 116 CNTRSTL 51 V DD 115 VDD 52 V SS 114 VSS 53 R/WR 113 R/WL 54 OER 112 OEL 55 FT/PIPER 111 FT/PIPEL 56 V SS 110 VSS 57 I/O 17R 109 I/O 17L 58 I/O 16R 108 I/O 16L 59 I/O 15R 107 I/O 15L 60 I/O 14R 106 I/O 14L 61 V DD 105 VDD 62 V DD 104 VSS 63 O 13R I/ 103 I/O 13L 64