HIGH-SPEED 2.5V 70T3339/19/99S 512/256/128K X 18 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE 1.5ns setup to clock and 0.5ns hold on all control, data, Features: and address inputs 200MHz True Dual-Port memory cells which allow simultaneous Self-timed write allows fast cycle time access of the same memory location Separate byte controls for multiplexed bus and bus High-speed data access matching compatibility Commercial: 3.4 (200MHz)/3.6ns (166MHz)/ Dual Cycle Deselect (DCD) for Pipelined Output Mode 4.2ns (133MHz)(max.) 2.5V (100mV) power supply for core Industrial: 4.2ns (133MHz) (max.) LVTTL compatible, selectable 3.3V (150mV) or 2.5V Selectable Pipelined or Flow-Through output mode (100mV) power supply for I/Os and control signals on Counter enable and repeat features each port Dual chip enables allow for depth expansion without Industrial temperature range (-40C to +85C) is additional logic available at 133MHz Interrupt and Collision Detection Flags Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine Full synchronous operation on both ports pitch Ball Grid Array (fpBGA) 5ns cycle time, 200MHz operation (14Gbps bandwidth) Supports JTAG features compliant with IEEE 1149.1 Fast 3.4ns clock to data out Green parts available, see ordering information Data input, address, byte enable and control registers Functional Block Diagram UBL UBR LBL LBR FT/PIPEL 0a 1a 0b 1b 1b 0b 1a 0a FT/PIPER 1/0 1/0 b a ab R/WL R/WR CE0L CE0R 1 1 CE1L CE1R B B B B 0 W W W W 0 0 1 1 0 L L R R 1/0 1/0 Dout0-8 L OEL Dout0-8 R OER Dout9-17 L Dout9-17 R , 0a 1a 1b 0b 1a 0a 0b 1b 0/1 FT/PIPER FT/PIPEL 0/1 ab ba 512/256/128K x 18 MEMORY ARRAY I/O0L - I/O17L Din L I/O0R - I/O17R Din R , CLKR CLKL (1) (1) A18R A18L Counter/ Counter/ A0L A0R ADDR R ADDR L REPEATL Address Address REPEATR ADSR ADSL Reg. Reg. CNTENR CNTENL TDI TCK INTERRUPT CE0 TMS CE 0 R JTAG L COLLISION CE1 TDO TRST CE1 R L DETECTION R/WR R/WL LOGIC COL L COLR INT L INT R 5652 drw 01 (2) ZZ (2) ZZL ZZR CONTROL LOGIC NOTES: 1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC s for the IDT70T3399. 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. NOVEMBER 2019 1 DSC-5652/11 2019 Integrated Device Technology, Inc.70T3339/19/99S High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description: The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit tional or bidirectional data flow in bursts. An automatic power down feature, synchronous Dual-Port RAM. The memory array utilizes Dual-Port controlled by CE0 and CE1, permits the on-chip circuitry of each port to memory cells to allow simultaneous access of any address from both ports. enter a very low standby power mode. Registers on control, data, and address inputs provide minimal setup and The IDT70T3339/19/99 can support an operating voltage of either hold times. The timing latitude provided by this approach allows systems 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power to be designed with very short cycle times. With an input data register, the supply for the core of the device (VDD) is at 2.5V. IDT70T3339/19/99 has been optimized for applications having unidirec- 6.422