IDT5V9888T 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE 3.3V EEPROM IDT5V9888T PROGRAMMABLE CLOCK GENERATOR FEATURES: DESCRIPTION: Three internal PLLs The IDT5V9888 is a programmable clock generator intended for high Internal non-volatile EEPROM performance data-communications, telecommunications, consumer, and 2 JTAG and FAST mode I C serial interfaces networking applications. There are three internal PLLs, each individually Input Frequency Ranges: 1MHz to 400MHz programmable, allowing for three unique non-integer-related frequencies. Output Frequency Ranges: The frequencies are generated from a single reference clock. The LVTTL: up to 200MHz reference clock can come from one of the two redundant clock inputs. A LVPECL/ LVDS: up to 500MHz glitchless automatic or manual switchover function allows any one of the Reference Crystal Input with programmable oscillator gain and redundant clocks to be selected during normal operation. 2 programmable linear load capacitance The IDT5V9888 can be programmed through the use of the I C or JTAG Crystal Frequency Range: 8MHz to 50MHz interfaces. The programming interface enables the device to be pro- Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider grammed when it is in normal operation or what is commonly known as in- 10-bit post-divider blocks system programmable. An internal EEPROM allows the user to save and Fractional Dividers restore the configuration of the device without having to reprogram it on Two of the PLLs support Spread Spectrum Generation power-up. JTAG boundary scan is also implemented. capability Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback I/O Standards: divider. This allows the user to generate three unique non-integer-related Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS frequencies. The PLL loop bandwidth is programmable to allow the user Inputs - 3.3V LVTTL/ LVCMOS to tailor the PLL response to the application. For instance, the user can tune Programmable Slew Rate Control the PLL parameters to minimize jitter generation or to maximize jitter Programmable Loop Bandwidth Settings attenuation. Spread spectrum generation and fractional divides are Programmable output inversion to reduce bimodal jitter allowed on two of the PLLs. Redundant clock inputs with glitchless auto and manual There are 10-bit post dividers on five of the six output banks. Two of the switchover options six output banks are configurable to be LVTTL, LVPECL, or LVDS. The JTAG Boundary Scan other four output banks are LVTTL. The outputs are connected to the PLLs Individual output enable/disable via the switch matrix. The switch matrix allows the user to route the PLL Power-down mode outputs to any output bank. This feature can be used to simplify and optimize 3.3V VDD the board layout. In addition, each output s slew rate and enable/disable Available in TQFP and VFQFPN packages function can be programmed. The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JUNE 2010 1 c 2010 Integrated Device Technology, Inc. DSC 7044/13IDT5V9888T 3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR INDUSTRIAL TEMPERATURE RANGE FUNCTIONAL BLOCK DIAGRAM XTALOUT OSC. XTALIN/REFIN OUT1 P2 Divider 10-Bit /2 OUT2 P3 Divider PLL 0 10-Bit OUT3 /2 CLKIN (1) OUT4 P4 Divider PLL 1 10-Bit /2 (1) OUT4 (1) OUT5 PLL 2 P5 Divider SHUTDOWN/OE 10-Bit /2 (1) OUT5 P6 Divider WRITE ENABLE EEPROM 10-Bit OUT6 /2 GOUT0/TDO/ GIN4/CLK SEL LOSS LOCK Control Block for Multi-Purpose I/O, Programming, Features 2 I C/JTAG GOUT1/ LOSS CLKIN NOTE: 1. OUT4 and OUT5 pairs can be configured to be LVDS, LVPECL, or two single-ended LVTTL outputs. As LVTTL, OUT4 and OUT5 can be configured to be non-inverting. 2 GIN0/SDAT/TDI GIN2/TMS GIN1/SCLK/TCLK GIN3/TRST