Product Information

553SDCGI8

553SDCGI8 electronic component of Renesas

Datasheet
IDT Clock Buffer Low Skew 1 to 4 50fs 50ps 200 MHz

Manufacturer: Renesas
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 2.3992 ea
Line Total: USD 2.4

7749 - Global Stock
Ships to you between
Mon. 20 May to Wed. 22 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
10614 - WHS 1


Ships to you between Mon. 20 May to Wed. 22 May

MOQ : 1
Multiples : 1

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553SDCGI8
Renesas

1 : USD 2.323
10 : USD 2.0585
100 : USD 1.748
250 : USD 1.6445
500 : USD 1.4835
1000 : USD 1.265
3000 : USD 1.196

     
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Product Category
RoHS - XON
Icon ROHS
Series
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Brand
Factory Pack Quantity :
Cnhts
Hts Code
Mxhts
Product Type
Subcategory
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553S Low Skew 1 to 4 Clock Buffer Datasheet Description Features The 553S is a low skew, single input to four output, clock Low additive phase jitter RMS: 50fs buffer. The 553S has best in class additive phase Jitter of Extremely low skew outputs (50ps) sub 50 fsec. Low cost clock buffer IDT makes many non-PLL and PLL based low skew output Packaged in 8-SOIC and small 8-DFN package, Pb-free devices as well as Zero Delay Buffers to synchronize Input/Output clock frequency up to 200MHz clocks. Contact us for all of your clocking needs. Ideal for networking clocks Operating voltages: 1.8V to 3.3V Output Enable mode tri-states outputs Advanced, low power CMOS process Extended temperature range (-40C to +105C) 3.3V tolerant input clock Block Diagram Q0 Q1 ICLK Q2 Q3 Output Enable 2020 Renesas Electronics Corporation 1 January 6, 2020553S Datasheet Pin Assignments VDD 1 8 OE VDD 1 8 OE Q0 2 7 Q3 Q0 2 7 Q3 Q1 3 6 Q2 Q1 3 6 Q2 GND 4 5 ICLK GND 4 5 ICLK 8-pin SOIC 8-pin DFN Pin Descriptions Pin Pin Pin Pin Description Number Name Type 1 VDD Power Connect to +1.8V, +2.5V, or +3.3V. 2 Q0 Output Clock output 0. 3 Q1 Output Clock output 1. 4 GND Power Connect to ground. 5 ICLK Input Clock input. 6 Q2 Output Clock output 2. 7 Q3 Output Clock output 3. 8 OE Input Output Enable. Tri-states outputs when low. Connect to VDD for normal operation. External Components A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible. A 33 series terminating resistor may be used on each clock output if the trace is longer than 1 inch. To achieve the low output skew that the 553S is capable of, careful attention must be paid to board layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 series termination on one output (with 33 on the others) will cause at least 15ps of skew. 2020 Renesas Electronics Corporation 2 January 6, 2020

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
CEL (RENESAS)
ID4
IDT
IDT, Integrated Device Technology Inc
INTEGRATED DEVICE
INTEGRATED DEVICE TECHNOLOGY
INTEGRATED DEVICES TECH AID
Intersil
INTERSIL - FGC
Intersil(Renes as Electronics)
Intersil(Renesas Electronics)
ITS
REA
RENESAS
RENESAS (IDT)
RENESAS (INTERSIL)
Renesas / IDT
Renesas / Intersil
Renesas Electronics
Renesas Electronics America
RENESAS TECHNOLOGY

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