Product Specification PE64102 UltraCMOS Digitally Tunable Capacitor (DTC) 100 3000 MHz General Description The PE64102 is a DuNE-enhanced Digitally Tunable Features Capacitor (DTC) based on Peregrines UltraCMOS technology. DTC products provide a monolithically 3-wire (SPI compatible) 8-bit serial interface integrated impedance tuning solution for demanding with built-in bias voltage generation and RF applications. They also offer a linear capacitance stand-by mode for reduces power change versus tuning state and excellent harmonic consumption performance compared to varactor-based tunable TM DuNE -enhanced UltraCMOS device solutions. 5-bit 32-state Digitally Tunable Capacitor This highly versatile product can be mounted in series C = 1.88 pF 14.0 pF (7.4:1 tuning ratio) in or shunt configurations and uses a 3-wire (SPI discrete 391 fF steps compatible) serial interface. It has a high ESD rating of RF power handing (up to 26 dBm, 6 V RF) PK 2 kV HBM on all ports making this the ultimate in and high linearity integration and ruggedness. The DTC will be offered in a standard 12-lead 2.0 x 2.0 x 0.55 mm QFN High quality factor commercial package. Wide power supply range (2.3V to 3.6V) and low current consumption Peregrines DuNE technology enhancements deliver (typ. I = 30 A 2.8V) DD high linearity and exceptional harmonics performance. Optimized for shunt configuration, but can It is an innovative feature of the UltraCMOS process, also be used in series configuration providing performance superior to GaAs with the economy and integration of conventional CMOS. Excellent 2 kV HBM ESD tolerance on all pins Applications include: Figure 1. Functional Block Diagram Antenna tuning Tunable filters Phase shifters Impedance matching Figure 2. Package Type 12-lead 2 x 2 x 0.55 mm QFN 71-0066-01 Document No. DOC-25359-2 www.psemi.com 2012-2013 Peregrine Semiconductor Corp. All rights reserved. Page 1 of 13 PE64102 Product Specification Table 1. Electrical Specifications 25C, V = 2.8V DD Parameter Configuration Condition Min Typ Max Unit 7 Operating Frequency Range Both 100 3000 MHz 6 Minimum Capacitance Shunt State = 00000, 100 MHz (RF+ to Grounded RF-) -10% 1.88 +10% pF 6 Maximum Capacitance Shunt State = 11111, 100 MHz (RF+ to Grounded RF-) -10% 14.0 +10% pF 6 Tuning Ratio Shunt C /C , 100 MHz 7.4:1 max min 6 Step Size Shunt 5 bits (32 states), constant step size (100 MHz) 0.391 pF 470 582 MHz with L removed 50 s 1 6 Quality Factor (C ) Shunt 698 960 MHz, with L removed 50 min s 1710 2170 MHz, with L removed 28 s 470 582 MHz with L removed 25 s 1 6 ) Shunt removed Quality Factor (C 698 960 MHz, with L 20 max s 1710 2170 MHz, with L removed 5 s State 00000 4.7 7 Self Resonant Frequency Shunt GHz State 11111 1.6 470 582 MHz, Pin +26 dBm, 50 -36 dBm 6 Shunt 698 915 MHz, Pin +26 dBm, 50 -36 dBm 1710 1910 MHz, Pin +26 dBm, 50 -36 dBm 4 Harmonics (2 and 3 ) fo fo 470 582 MHz, Pin +20 dBm, 50 -36 dBm 5 Series 698 915 MHz, Pin +20 dBm, 50 -36 dBm 1710 1910 MHz, Pin +20 dBm, 50 -36 dBm IIP3 = (Pblocker + 2*Ptx - IMD3 ) / 2, where IMD3 = -95 dBm, 6 3rd Order Intercept Point Shunt 60 dBm Ptx = +20 dBm and Pblocker = -15 dBm State change to 10/90% delta capacitance between only two 2, 3 6 Switching Time Shunt 2 10 s states 2 6 Time from V within specification to all performances within DD Start-up Time Shunt 5 20 s specification State change from standby mode to RF state to all 2,3 6 Wake-up Time Shunt 5 20 s performances within specification Note: 1. Q for a Shunt DTC based on a Series RLC equivalent circuit Q = X / R = (X-X ) / R, where X = X + X , X = 2*pi*f*L, X = -1 / (2*pi*f*C), which is equal to removing the effect of parasitic inductance L C L L C L C S 2. DC path to ground at RF+ and RF must be provided to achieve specified performance 3. State change activated on falling edge of SEN following data word 4. Between 50 ports in series or shunt configuration using a pulsed RF input with 4620 vs period, 50% duty cycle, measured per 3GPPTS45.005 5. In series configuration the greater RF power or higher RF voltage should be applied to RF+ 6. RF- should be connected to ground 7. DTC operation above SRF is possible 2012-2013 Peregrine Semiconductor Corp. All rights reserved. Document No. DOC-25359-2 UltraCMOS RFIC Solutions Page 2 of 13