PE42822 Document Category: Product Specification UltraCMOS SPDT RF Switch, 700 MHz3.8 GHz Features Figure 1 PE42822 Functional Diagram Excellent single-event peak power handling of 46.1 dBm LTE RFC Exceptional linearity performance across all frequencies Input IP3: 65 dBm RF1 RF2 Input IP2: 120 dBm Extended operating temperature of 105 C 1.8V/3.3V TTL compatible control 50 50 High ESD performance of 3 kV HBM on RF pins to ground CMOS Control Driver and ESD Packaging 16-lead 3 3 0.85 mm QFN LS CTRL V DD Applications Wireless infrastructure Receiver protection switch Product Description The PE42822 is a HaRP technology-enhanced absorptive 50 SPDT RF protection switch designed for use in high power and high performance wireless infrastructure applications such a mid-power microcell products, supporting frequencies up to 3.8 GHz. This switch features high linearity, which remains invariant across the full supply range. The PE42822 also features exceptional isolation, fast switching time and is offered in a 16-lead 3 3 mm QFN package. In addition, no external blocking capacitors are required if 0 VDC is present on the RF ports. The PE42822 is manufactured on Peregrines UltraCMOS process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate. Peregrines HaRP technology enhancements deliver high linearity and excellent harmonics performance. It is an innovative feature of the UltraCMOS process, offering the performance of GaAs with the economy and integration of conventional CMOS. 2015, Peregrine Semiconductor Corporation. All rights reserved. Headquarters: 9380 Carroll Park Drive, San Diego, CA, 92121 Product Specification DOC-67330-2 (09/2015) www.psemi.comPE42822 SPDT RF Switch Absolute Maximum Ratings Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for extended periods may reduce reliability. ESD Precautions When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rating specified in Table 1. Latch-up Immunity Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up. Table 1 Absolute Maximum Ratings for PE42822 Parameter/Condition Min Max Unit Supply voltage, V 0.3 5.5 V DD Digital input voltage, V 0.3 3.6 V CTRL LS input voltage 0.3 3.6 V (1) Maximum input power, P PK 46.1 dBm 7003800 MHz Storage temperature range 65 +150 C (2) ESD voltage HBM 3000 V RF pins to GND 1500 V All pins (3) 200 V ESD voltage MM , all pins (4) 1000 V ESD voltage, CDM , all pins Notes: 1) Max 5 cycles at 10 seconds duration each cycle, P = 46.1 dBm, P = 38.1 dBm, 8 dB PAR LTE signal. All other parameters within recom- PK AV mended operating conditions. No power applied to off-terminated port. No hot switching. 2) Human body model (MIL STD 883 Method 3015). 3) Machine model (JEDEC JESD22 A115). 4) Charged device model (JEDEC JESD22-C101). Page 2 DOC-67330-2 (09/2015) www.psemi.com