NBC12439, NBC12439A 3.3V/5VProgrammable PLL Synthesized Clock Generator 50 MHz to 800 MHz NBC12439, NBC12439A PWR DOWN +3.3 or 5.0 V 2 1 PLL V CC F REF PHASE POWER 2 DETECTOR DOWN +3.3 or 5.0 V 15 XTAL SEL VCO 21, 25 3 V FREF EXT CC 24 FOUT 7 BIT M N 4 23 2 XTAL1 COUNTER (1, 2, 4, 8) FOUT 400 800 MHz 10 20MHz OSC 20 5 TEST XTAL2 LATCH LATCH 6 OE 28 S LOAD LATCH 7 P LOAD 01 01 27 S DATA 2BIT SR 3BIT SR 7BIT SR 26 S CLOCK 8 14 17, 18 22, 19 7 2 M 6:0 N 1:0 Figure 1. Block Diagram (28Lead PLCC) Table 1. Output Division Table 2. XTAL SEL And OE N 1:0 Output Division Input 0 1 0 0 2 PWR DOWN F F 16 OUT OUT 0 1 4 XTAL SEL FREF EXT XTAL 1 0 8 OE* Outputs Disabled Outputs Enabled 1 1 1 *When disabled, FOUT goes LOW, FOUT goes HIGH.