NB7V58M 1.8 V / 2.5 V / 3.3 V Differential 2:1 Clock / Data Multiplexer / Translator with CML Outputs NB7V58M Exposed MultiLevel Inputs VT0 GND GND VCC Pad (EP) LVPECL, LVDS, CML IN0 16 15 14 13 50 0 VT0 IN0 1 12 Q 50 IN0 Q 2 11 IN0 GND 2:1 NB7V58M Mux IN1 Q IN1 3 10 GND 50 1 VT1 IN1 4 9 Q 50 VCC IN1 56 7 8 25 k VT1 SEL NC VCC SEL Figure 1. Pin Configuration (Top View) Figure 2. Detailed Block Diagram Table 1. SELect FUNCTION TRUTH TABLE SEL Q Q L IN0 IN0 H IN1 IN1 Table 2. PIN DESCRIPTION Pin Name I/O Description 1 IN0 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1) 2 IN0 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1) 3 IN1 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1) 4 IN1 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1) 5 VT1 Internal 50 Termination Pin for IN1/IN1 6 SEL LVTTL/LVCMOS Input SEL Input. Low for IN0 inputs, high for IN1 inputs. (Note 1) Pin will default HIGH when left open (has internal pull up resistor) 7 NC No Connect 8 VCC Positive Supply Voltage (Note 2) 9 Q CML Output Inverted Differential Output 10 GND Negative Supply Voltage 11 GND Negative Supply Voltage 12 Q CML Output Noninverted Differential Output 13 VCC Positive Supply Voltage (Note 2) 14 GND Negative Supply Voltage 15 GND Negative Supply Voltage 16 VT0 Internal 50 Termination Pin for IN0/IN0 EP The Exposed Pad (EP) on the QFN 16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heatsinking conduit. The pad is electrically connected to the die, and must be elec- trically and thermally connected to GND on the PC board. 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on IN0/IN0, IN1/IN1 inputs, then the device will be susceptible to selfoscillation. Q/Q outputs have internal 50 source termination resistors. 2. All VCC and GND pins must be externally connected to a power supply for proper operation.