NB7L11M 2.5 V/3.3 V Differential 1:2 Clock/Data Fanout Buffer/Translator with CML Outputs and Internal www.onsemi.com Termination Description The NB7L11M is a differential 1-to-2 clock/data distribution chip with internal source termination and CML output structure, optimized for low skew and minimal jitter. The device is functionally equivalent to 1 the EP11, LVEP11, or SG11 devices. Device produces two identical QFN16 output copies of clock or data operating up to 8GHz or 12Gb/s, MN SUFFIX respectively. As such, NB7L11M is ideal for SONET, GigE, Fiber CASE Channel, Backplane and other clock/data distribution applications. 485G01 Inputs incorporate internal 50 termination resistors and accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6). Differential 16 mA CML output provides matching internal 50 terminations, and 400 mV output swings when externally terminated, MARKING DIAGRAM* 50 to V (See Figure 14). CC The device is offered in a low profile 3x3 mm 16-pin QFN package. NB7L Application notes, models, and support documentation are available at 11M www.onsemi.com. ALYW Features Maximum Input Clock Frequency up to 8 GHz Typical A = Assembly Location Maximum Input Data Rate up to 12 Gb/s Typical L = Wafer Lot Y = Year < 0.5 ps of RMS Clock Jitter W = Work Week < 10 ps of Data Dependent Jitter = Pb-Free Package 30 ps Typical Rise and Fall Times (Note: Microdot may be in either location) 110 ps Typical Propagation Delay *For additional marking information, refer to 3 ps Typical Within Device Skew Application Note AND8002/D. Operating Range: V = 2.375 V to 3.465 V with V = 0 V CC EE CML Output Level (400 mV Peak-to-Peak Output) Differential Output Only 50 Internal Input and Output Termination Resistors ORDERING INFORMATION Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP Device Package Shipping and SG Devices NB7L11MMNG QFN16 123 Units/Tube These Devices are Pb-Free, Halogen Free and are RoHS Compliant (Pb-Free) NB7L11MMNR2G QFN16 3000/Tape & Reel Q0 V TCLK (Pb-Free) Q0 50 For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer CLK to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. CLK 50 Q1 V TCLK Q1 Figure 1. Logic Diagram Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 Rev. 4 NB7L11M/DNB7L11M Exposed Pad (EP) V Q0 Q0 V CC CC 16 15 14 13 V 1 12 V TCLK EE CLK 2 11 V EE NB7L11M CLK V 3 10 EE V V TCLK 4 9 EE 56 7 8 V Q1 Q1 V CC CC Figure 2. QFN16 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1 V Internal 50 Termination Pin for CLK TCLK 2 CLK LVPECL, CML, Inverted Differential Clock/Data Input. (Note 1) LVCMOS, LVTTL, LVDS 3 CLK LVPECL, CML, Noninverted Differential Clock/Data Input. (Note 1) LVCMOS, LVTTL, LVDS 4 V Internal 50 Termination Pin for CLK TCLK 5,8,13,16 V Positive Supply Voltage. All V pins must be externally connected to a Power Supply CC CC to guarantee proper operation. 6 Q1 CML Output Inverted CLK output 1 with internal 50 source termination resistor. (Note 2) 7 Q1 CML Output Noninverted CLK output 1 with internal 50 source termination resistor. (Note 2) 9,10,11,12 V Negative Supply Voltage. All V pins must be externally connected to a Power Supply EE EE to guarantee proper operation. 14 Q0 CML Output Inverted CLK output 0 with internal 50 source termination resistor. (Note 2) 15 Q0 CML Output Noninverted CLK output 0 with internal 50 source termination resistor. (Note 2) EP Exposed Pad. The thermally exposed pad on package bottom (see case drawing) must be attached to a heatsinking conduit. It is recommended to connect the EP to the lower potential (V ). EE 1. In the differential configuration when the input termination pins (V , V ) are connected to a common termination voltage or left open, TCLK TCLK and if no signal is applied on CLK and CLK then the device will be susceptible to self-oscillation. 2. CML outputs require 50 receiver termination resistor to V for proper operation. CC www.onsemi.com 2