Product Information

NB4L7210MNG

NB4L7210MNG electronic component of ON Semiconductor

Datasheet
Clock Divider 52-Pin QFN EP Rail

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

20: USD 21.8673 ea
Line Total: USD 437.35

0 - Global Stock
MOQ: 20  Multiples: 20
Pack Size: 20
Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 24 May to Thu. 30 May

MOQ : 20
Multiples : 20

Stock Image

NB4L7210MNG
ON Semiconductor

20 : USD 21.8673

0 - WHS 2


Ships to you between Fri. 24 May to Thu. 30 May

MOQ : 260
Multiples : 260

Stock Image

NB4L7210MNG
ON Semiconductor

260 : USD 21.7181

     
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RoHS - XON
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NB4L7210 2.5V/3.3V Differential 2x10 Crosspoint Clock Driver with SDI Programmable Output Selects NB4L7210 Exposed Pad (EP) 52 51 50 49 48 47 46 45 44 43 42 41 40 GND 1 39 VCC3 SLOAD 2 38 Q3 VTCLK0 3 37 Q3 CLK0 4 36 VCC4 CLK0 5 35 Q4 VTCLK0 6 34 Q4 NB4L7210 GND 7 33 GND VTCLK1 8 32 Q5 CLK1 9 31 Q5 CLK1 10 30 VCC5 VTCLK1 11 29 Q6 SDATA 12 28 Q6 GND 13 27 VCC6 14 15 16 17 18 19 20 21 22 23 24 25 26 Figure 2. Pin Configuration (Top View) Table 1. PIN DESCRIPTION Pin Name I/O Description 1, 7, 13, 25, 26, 33, GND Supply Negative Supply pins must be all externally connected to a power 40, 41 supply to guarantee proper operation. 2 SLOAD LVCMOS, LVTTL Serial Load and Latch control input pin. Defaults LOW when float- ing open. 3, 6, 8, 11 VTCLK0, VTCLK0, Termination Internal 50 Ohms Termination Resistor connection Pins. In the VTCLK1, VTCLK1 differential configuration when the input termination pins are con- nected to the common termination voltage. 4, 9 CLK0, CLK1 Differential LVPECL, CLOCK Input (TRUE). If no signal is applied then the device may CML, or LVDS be susceptible to self oscillation. 5, 10 CLK0, CLK1 Differential LVPECL, CLOCK Input (INVERT). If no signal is applied then the device CML, or LVDS may be susceptible to self oscillation. 12 SDATA LVCMOS, LVTTL Serial Data input pin (for BITS 0:9, a 0 selects CLK1, 1 selects CLK 0). Defaults LOW when floating open. 14 SCLK LVCMOS, LVTTL Serial Load Clock input pin. Defaults LOW when floating open. 15, 16, 19, 22, 27, VCC, VCC9, VCC8, Supply Positive Supply pins must be all externally connected to a power 30, 36, 39, 44, 47, VCC7, VCC6, VCC5, supply to guarantee proper operation. 50, 51 VCC4, VCC3, VCC2, VCC1, VCC0 17, 20, 23, 28, 31, Q 90 LVPECL Output (INVERT) 34, 37, 42, 45, 48 18, 21, 24, 29, 32, Q 90 LVPECL Output (TRUE) 35, 38, 43, 46, 49 52 SDATAOUT LVCMOS, LVTTL Serial Data output pin for cascade Exposed Pad EP GND Exposed Pad. The thermally exposed pad (EP) on package bot- tom (see case drawing) must be attached to a sufficient heat sinking conduit for proper thermal operation and must be connec- ted to GND.

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Aptina / ON Semiconductor
FAIRCHILD
FAIRCHILD (ON SEMICONDUCTOR)
Fairchild Semiconductor
FS8
FSC
ON
ON SEMI
ON Semicon
ON SEMICONDUCTOR
ON SEMICONDUCTOR (FAIRCHILD)
ON Semiconductor / Fairchild
ON4
ON5
onsemi
ON-SEMI
onsemi / Fairchild
OOF
Xsens / Fairchild

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