3.3 V 100/133 MHz Differential 1:8 HCSL- Compatible Push-Pull Clock ZDB/Fanout Buffer for PCIe NB3W800L www.onsemi.com Description MARKING The NB3W800L is a lowpower 8output differential buffer that DIAGRAM meets all the performance requirements of the DB800ZL specification. The NB3W800L is capable of distributing the reference 1 clocks for Intel QuickPath Interconnect (Intel QPI and UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel Scalable Memory NB3W800L 1 48 AWLYYWWG Interconnect (Intel SMI) applications. A fixed, internal feedback path CASE 485DP maintains low drift for critical QPI applications. Features NB3W800L = Specific Device Code 8 Differential Clock Output Pairs 0.7 V A = Assembly Location Lowpower NMOS Pushpull HCSL Compatible Outputs WL = Wafer Lot YY = Year Cycletocycle Jitter <50 ps WW = Work Week Outputtooutput Skew <50 ps G = PbFree Package Inputtooutput Delay Variation <100 ps PCIe Phase Jitter: Gen3 <1.0 ps, Gen4 <0.5 ps RMS ORDERING INFORMATION QPI 9.6GT/s 12UI Phase Jitter <0.2 ps RMS Device Package Shipping* PseudoExternal Fixed Feedback for Lowest InputtoOutput Delay NB3W800LMNG QFN48 490 / Tray Individual OE Control Hardware Control of Each Output (PbFree) PLL Configurable for PLL Mode or Bypass Mode (Fanout NB3W800LMNTXG QFN48 2500 / Tape & Operation) (PbFree) Reel 100 MHz or 133 MHz PLL Mode Operation Supports PCIe, QPI *Pin 1 in upper left corner of Tape and Reel and UPI Applications Selectable PLL Bandwidth Minimizes Jitter Peaking in Downstream PLLs SMBus Programmable Configurations Spread Spectrum Compatible Tracks Input Clock Spreading for Low EMI These are PbFree Devices Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: August, 2020 Rev. 4 NB3W800L/DNB3W800L 8 OE 7:0 FB OUT FB OUT DIF 7:0 SSC Compatible MUX PLL DIF 7:0 CLK IN CLK IN 100M 133M HBW BYP LBW Control Logic PWRGD/PWRDN SDA SCL Figure 1. Simplified Block Diagram Table 1. OE AND POWER PIN TABLE Inputs OE Hardware Pins & Control Register Bits Outputs PWRGD/ CLK IN/ SMBUS FB OUT/ PWRDN CLK IN Enable Bit FB OUT OE Pin DIF/DIF 7:0 PLL State 0 X X X HiZ HiZ OFF 1 Running 0 X HiZ Running ON 1 0 Running Running ON 1 1 HiZ Running ON Table 2. FUNCTIONALITY AT POWERUP (PLL MODE) Table 5. PLL OPERATING MODE READBACK TABLE 100M 133M CLK IN MHz DIF(7:0) HBW BYP LBW Byte0, bit 7 Byte 0, bit 6 1 100.00 CLK IN Low (Low BW) 0 0 0 133.33 CLK IN Mid (Bypass) 0 1 High (High BW) 1 1 Table 3. POWER CONNECTIONS Table 6. TRILEVEL INPUT THRESHOLDS Pin Number Level Voltage VDD GND Description Low <0.8 V 44 49 Analog PLL Mid 1.2<Vin<1.8 V 3 2 Analog Input High Vin > 2.2 V 10, 15, 19, 27, 34, 38, 42 49 DIF clocks Table 7. PLL OPERATING MODE Table 4. SMBus ADDRESS HBW BYP LBW Mode Address + Read/Write bit Low PLL Lo BW D8 R Mid Bypass High PLL Hi BW NOTE: PLL is OFF in Bypass Mode www.onsemi.com 2