2.5V / 3.3V Low Noise Multi-Rate Clock Generator NB3H5150-01 Description The NB3H515001 is a high performance MultiRate Clock generator which simultaneously synthesizes up to four different www.onsemi.com frequencies from a single PLL using a 25 MHz input reference. The reference frequency can be provided by a crystal, LVCMOS/LVTTL, MARKING LVPECL, HCSL or LVDS differential signals. The REFMODE pin DIAGRAM* will select the reference source. 1 Three output banks (CLK1A/CLK1B to CLK3A/CLK3B) produce QFN32 NB3H user selectable frequencies of: 33.33 MHz, 50 MHz, 100 MHz, MN SUFFIX 515001 125 MHz, or 156.25 MHz and have ultralow noise/jitter performance CASE 485CE AWLYYWWG 1 32 of less than 0.3 ps. The fourth output bank (CLK4A/CLK4B) can produce the following integer and FRACN frequencies in pinstrap mode: A = Assembly Location 25 MHz, 33.33 MHz, 66.66 MHz, 100 MHz, 125 MHz, 133.33 MHz, WL = Wafer Lot 156.25 MHz or 161.1328 MHz. YY = Year Each output block can create two singleended inphase LVCMOS WW = Work Week outputs or one differential pair of LVPECL outputs. G = PbFree Package Each of the four output blocks is independently powered by a *For additional marking information, refer to separate VDDO, 2.5 V/3.3 V for LVPECL, 1.8 V/2.5 V/3.3 V for Application Note AND8002/D. LVCMOS. 2 The serial (I C and SMBUS) interface can be used to load register files into the NB3H515001 to program a variety of functions ORDERING INFORMATION including the frequencies and output levels of each output which can See detailed ordering and shipping information on page 18 of be individually enabled and disabled. this data sheet. Features Flexible Input Reference 25 MHz Crystal, Oscillator, 1 ps maximum RMS Phase Jitter FRACN (CLK4) SingleEnded or Differential Clock 161.1328 MHz 2 Four Independent UserProgrammable Clock I C / SMBus Compatible Interface Frequencies from 25 MHz to 250 MHz 40C to +85C Ambient Operating Temperature Independently Configurable Outputs: Zero ppm Multiplication Error Up to Eight LVCMOS Single Ended outputs or, Fractional Divide Ratios for Implementing Arbitrary Up to Four Differential LVPECL Outputs or any FEC/InverseFEC Ratios combination of LVCMOS and LVPECL For Additional Pinstrap Frequency and Output Type Flexible Input/Core and Output Power Supply Combinations, Contact ON Semiconductor Sales Office Combinations: 32Pin QFN, 5 mm x 5 mm VDD (Core) = 3.3 V 5% or 2.5 V 5% This is a PbFree Device VDDO (Outputs) = 3.3 V 5% or 2.5 V 5% or n 1.8 V 5% (LVCMOS Only) Applications Independent Power Supply for each Output Bank Telecom 300 ps max Output Rise and Fall Times, LVPECL Networking 1000 ps max Output Rise and Fall Times, LVCMOS Ethernet 300 fs maximum RMS Phase Jitter IntergerN SONET (CLK1:4) 156.25 MHz Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2020 Rev. 4 NB3H515001/DNB3H515001 VDD AVDD1 AVDD2 AVDD3 REF (I2C Mode) VDDO1 CLK XTAL1 XTAL PLL Integer N OSC CLK1A DIV1 CLK XTAL2 CLK1B VDDO2 Integer N CLK2A DIV2 CLK2B VDDO3 SDA Integer N CLK3A DIV3 SCL/PD CLK3B Configuration Table MMC & VDDO4 I2C Interface Integer N or REFMODE CLK4A Fractional N CLK4B LDOs DIV4 FTM LDO2 LDO1 LDO3 LDO4 Figure 1. Simplified Block Diagram of NB3H5150 01 Exposed Pad (EP) 32 31 30 29 28 27 26 25 CLK XTAL2 1 24 FTM 2 23 CLK2B REFMODE CLK2A 22 3 SDA SCL/PD 4 21 VDDO2 NB3H515001 5 20 VDD VDDO3 FS1 6 19 CLK3A 7 FS2 18 CLK3B FS3 8 17 MMC 9 10 11 12 13 14 15 16 Figure 2. 32Lead QFN Pinout (Top View) www.onsemi.com 2 FS1 FS2 FS3 CLK XTAL1 FS4A FS4A LDO1 FS4B FS4B AVDD1 LDO4 AVDD3 LDO2 LDO3 AVDD2 CLK4A CLK1A CLK1B CLK4B VDDO4 VDDO1