MM74HC4514 4-to-16 Line Decoder with Latch
February 1984
Revised July 2003
MM74HC4514
4-to-16 Line Decoder with Latch
General Description Features
The MM74HC4514 utilizes advanced silicon-gate CMOS Typical propagation delay: 18 ns
technology, which is well suited to memory address decod-
Low quiescent power: 80 A maximum (74HC Series)
ing or data routing application. It possesses high noise
Low input current: 1 A maximum
immunity and low power dissipation usually associated with
Fanout of 10 LS-TTL loads (74HC Series)
CMOS circuitry, yet speeds comparable to low power
Schottky TTL circuits. It can drive up to 10 LS-TTL loads.
The MM74HC4514 contain a 4-to-16 line decoder and a 4-
bit latch. The latch can store the data on the select inputs,
thus allowing a selected output to remain HIGH even
though the select data has changed. When the LATCH
ENABLE input to the latches is HIGH the outputs will
change with the inputs. When LATCH ENABLE goes LOW
the data on the select inputs is stored in the latches. The
four select inputs determine which output will go HIGH pro-
vided the INHIBIT input is LOW. If the INHIBIT input is
HIGH all outputs are held LOW thus disabling the decoder.
The MM74HC4514 is functionally and pinout equivalent to
the CD4514BC and the MC1451BC. All inputs are pro-
tected against damage due to static discharge diodes from
V and ground.
CC
Ordering Code:
Order Number Package Number Package Description
MM74HC4514WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC4514MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC4514N N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
2003 Fairchild Semiconductor Corporation DS005215 www.fairchildsemi.comConnection Diagram Truth Table
Data Inputs
LE Inhibit D C B A Selected
Output
High
H L LL LL S0
HL L L L H S1
HL L L H L S2
HL L L H H S3
HL L H L L S4
H L LH LH S5
HL L H H L S6
HL L H H H S7
HL H L L L S8
HL H L L H S9
HL H L H L S10
HL H L H H S11
HL H H L L S12
Top View HL H H L H S13
H L HHH L S14
H L HHH H S15
All
X H XX XX Outputs = 0
Latched
L L XX XX Data
Logic Diagram
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MM74HC4514