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Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.MM74HC175 Quad D-Type Flip-Flop With Clear September 1983 Revised February 1999 MM74HC175 Quad D-Type Flip-Flop With Clear The 74HC logic family is functionally as well as pin-out General Description compatible with the standard 74LS logic family. All inputs The MM74HC175 high speed D-type flip-flop with comple- are protected from damage due to static discharge by inter- mentary outputs utilizes advanced silicon-gate CMOS nal diode clamps to V and ground. CC technology to achieve the high noise immunity and low power consumption of standard CMOS integrated circuits, Features along with the ability to drive 10 LS-TTL loads. Typical propagation delay: 15 ns Information at the D inputs of the MM74HC175 is trans- ferred to the Q and Q outputs on the positive going edge of Wide operating supply voltage range: 26V the clock pulse. Both true and complement outputs from Low input current: 1 A maximum each flip flop are externally available. All four flip-flops are Low quiescent supply current: 80 A maximum (74HC) controlled by a common clock and a common CLEAR. High output drive current: 4 mA minimum (74HC) Clearing is accomplished by a negative pulse at the CLEAR input. All four Q outputs are cleared to a logical 0 and all four Q outputs to a logical 1. Ordering Code: Order Number Package Number Package Description MM74HC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow MM74HC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Truth Table (Each Flip-Flop) Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Outputs Clear Clock D Q Q LX XL H H HH L H LL H HL XQ Q 0 0 H = HIGH Level (steady state) L = LOW Level (steady state) X = Irrelevant = Transition from LOW-to-HIGH level Q = The level of Q before the indicated steady-state input conditions were 0 established Top View 1999 Fairchild Semiconductor Corporation DS005319.prf www.fairchildsemi.com