Ships to you between Thu. 23 May to Wed. 29 May
MC74VHC157DR2G ON Semiconductor
Ships to you betweenThu. 30 May to Tue. 04 Jun
Ships to you between Wed. 29 May to Fri. 31 May
ON Semiconductor Logic Gates 2-5.5V Single NAND 2-Input wOpen Drain Stock : 2790
Logic Gates 2-5.5V Single NOR 2-Input Stock : 546
Logic Gates 2-5.5V Single NAND 2-Input w/Open Drain Stock : 2558
Logic Gates 2-5.5V Single 2-Input NAND Stock : 21000
Logic Gates 2-5.5V Single NOR 2-Input Stock : 6887
Logic Gates 2-5.5V Single NAND 2-Input w/Open Drain Stock : 3223
Logic Gates 2-5.5V Single 2-Input NAND Stock : 248
Logic Gates 2-5.5V Single 2-Input NAND Stock : 0
Encoders, Decoders, Multiplexers & Demultiplexers 2-5.5V Quad 2-Channel Stock : 3295
NAND Gate CMOS 2-Input 2V to 5.5V 5-Pin SC-74A Surface Mount T/R Stock : 8592
High Speed Operational Amplifiers Low-Pwr ADSL Cent-Office Line Drv Stock : 0
High Speed Operational Amplifiers High Speed Stock : 0
ADSL Receiver Dual 8-Pin HVSSOP EP T/R Stock : 0
High Speed Operational Amplifiers Low-Noise ADSL Dual Diff Receiver Stock : 0
High Speed Operational Amplifiers 275-mA +12V ADSL CPE Line Driver Stock : 60
High Speed Operational Amplifiers 275-mA +12V ADSL CPE Line Drv w/Shutdown Stock : 0
High Speed Operational Amplifiers 275-mA +12V ADSL CPE Line Drv w/Shutdown Stock : 85
High Speed Operational Amplifiers High Eff Class-G ADSL Line Driver Stock : 0
High Speed Operational Amplifiers Low Pwr Dissipation Line Driver Stock : 109
MC74VHC157 Quad 2-Channel Multiplexer The MC74VHC157 is an advanced highspeed CMOS quad 2 channel multiplexer, fabricated with silicon gate CMOS technology. It achieves highspeed operation similar to equivalent Bipolar Schottky TTL, while maintaining CMOS low power MC74VHC157 2 A0 4 3 Y0 B0 5 A1 7 6 Y1 B1 NIBBLE DATA 11 INPUTS A2 OUTPUTS 9 10 Y2 B2 14 A3 12 Y3 13 B3 15 E 1 S Figure 2. Expanded Logic Diagram 15 E EN 1 S G1 2 A0 MUX 1 4 Y0 3 B0 1 5 A1 7 Y1 6 B1 11 A2 9 Y2 10 B2 14 A3 12 Y3 13 B3 Figure 3. IEC Logic Symbol FUNCTION TABLE Inputs Outputs E SY0 Y3 H X L L L A0 A3 L H B0 B3 A0 A3, B0 B3 = the levels of the respective DataWord Inputs.
