MC74HCT138ADR2G

MC74HCT138A 1-of-8 Decoder/ Demultiplexer with LSTTL Compatible Inputs HighPerformance SiliconGate CMOS www.onsemi.com The MC74HCT138A is identical in pinout to the LS138. The HCT138A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The HCT138A decodes a threebit Address to oneofeight SOIC16 TSSOP16 activelot outputs. This device features three Chip Select inputs, two D SUFFIX DT SUFFIX activelow and one activehigh to facilitate the demultiplexing, CASE 751B CASE 948F cascading, and chipselecting functions. The demultiplexing function is accomplished by using the Address inputs to select the desired PIN ASSIGNMENT device output one of the Chip Selects is used as a data input while the A0 1 16 other Chip Selects are held in their active states. V CC 2 15 A1 Y0 Features 3 14 A2 Y1 Output Drive Capability: 10 LSTTL Loads 4 13 CS2 Y2 TTL/NMOS Compatible Input Levels 5 12 CS3 Y3 Outputs Directly Interface to CMOS, NMOS, and TTL 6 11 CS1 Y4 Operating Voltage Range: 2 to 6 V 7 10 Y7 Y5 Low Input Current: 1.0 A GND Y6 8 9 In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 122 FETs or 30.5 Equivalent Gates MARKING DIAGRAMS These Devices are PbFree, Halogen Free/BFR Free and are RoHS 16 Compliant HCT138AG LOGIC DIAGRAM AWLYWW 1 1 15 SOIC16 A0 Y0 ADDRESS 2 14 A1 Y1 INPUTS 16 3 13 A2 Y2 HCT 138A 12 Y3 ALYW ACTIVE-LOW 11 OUTPUTS Y4 1 10 Y5 TSSOP16 9 Y6 A = Assembly Location 7 Y7 WL, L = Wafer Lot YY, Y = Year WW, W = Work Week 6 G or = PbFree Package CS1 CHIP- 4 PIN 16 = V (Note: Microdot may be in either location) CC SELECT CS2 PIN 8 = GND INPUTS 5 CS3 ORDERING INFORMATION See detailed ordering and shipping information on page 5 of this data sheet. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: June, 2015 Rev. 11 MC74HCT138A/DMC74HCT138A Design Criteria Value Units Internal Gate Count* 30.5 ea. Internal Gate Propagation Delay1.5 ns Internal Gate Power Dissipation 5.0 W Speed Power Product .0075 pJ *Equivalent to a twoinput NAND gate. FUNCTION TABLE Inputs Outputs CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X HHHHHHH H X H X X X X HHHHHHH H L X X X X X HHHHHHH H H L L L L L L HHHHHH H H L L L L H H L HHHHH H H L L L H L HH L HHHH H H L L L H H HHH L HHH H H L L H L L HHHH L H H H H L L H L H HHHHH L H H H L L H H L HHHHHH L H H L L H H H HHHHHHH L H = high level (steady state) L = low level (steady state) X = dont care MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage V DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V CC due to high static voltages or electric V DC Input Voltage (Referenced to GND) 0.5 to V + 0.5 V in CC fields. However, precautions must be taken to avoid applications of any V DC Output Voltage (Referenced to GND) 0.5 to V + 0.5 V out CC voltage higher than maximum rated I DC Input Current, per Pin 20 mA voltages to this highimpedance cir- in cuit. For proper operation, V and in I DC Output Current, per Pin 25 mA out V should be constrained to the out I DC Supply Current, V and GND Pins 50 mA range GND (V or V ) V . CC CC in out CC Unused inputs must always be P Power Dissipation in Still Air SOIC Package 500 mW D tied to an appropriate logic voltage TSSOP Package 450 level (e.g., either GND or V ). CC Unused outputs must be left open. T Storage Temperature 65 to +150 C stg T Lead Temperature, 1 mm from Case for 10 Seconds C L (TSSOP or SOIC Package) 260 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Derating: SOIC Package: 7 mW/ C from 65 to 125 C TSSOP Package: 6.1 mW/ C from 65 to 125 C www.onsemi.com 2