MC74HC595A 8-Bit Serial-Input/Serial or Parallel-Output Shift Register with Latched 3-State Outputs www.onsemi.com HighPerformance SiliconGate CMOS The MC74HC595A consists of an 8bit shift register and an 8bit Dtype latch with threestate parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also SOIC16 TSSOP16 provides parallel data to the 8bit latch. The shift register and latch D SUFFIX DT SUFFIX have independent clock inputs. This device also has an asynchronous CASE 751B CASE 948F reset for the shift register. The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs. 1 QFN16 Features MN SUFFIX CASE 485AW Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL MARKING DIAGRAMS Operating Voltage Range: 2.0 to 6.0 V 16 Low Input Current: 1.0 A 16 HC High Noise Immunity Characteristic of CMOS Devices 595A HC595AG In Compliance with the Requirements Defined by JEDEC ALYW AWLYWW Standard No. 7 A 1 1 Chip Complexity: 328 FETs or 82 Equivalent Gates SOIC16 TSSOP16 Improvements over HC595 Improved Propagation Delays 595A ALYW 50% Lower Quiescent Power Improved Input Noise and Latchup Immunity QFN16* NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ100 *V595A marking used for NLV74HC595AMN1TWG Qualified and PPAP Capable These Devices are PbFree, Halogen Free and are RoHS Compliant A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G, = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: December, 2016 Rev. 23 MC74HC595A/DMC74HC595A Q V B CC Q 1 16 V B CC 116 Q 2 15 Q C A Q215 Q C A Q 3 14 A D 314 Q A D Q 4 13 OUTPUT ENABLE E 413 OUTPUT ENABLE Q E GND Q 5 12 LATCH CLOCK F Q512 LATCH CLOCK F Q 6 11 SHIFT CLOCK G Q611 SHIFT CLOCK G Q 7 10 RESET H Q710 RESET H 89 GND 8 9 SQ H GND SQ H SOIC, TSSOP QFN Figure 1. Pin Assignments LOGIC DIAGRAM SERIAL 14 15 DATA A Q A 1 INPUT Q B 2 Q C 3 PARALLEL Q D DATA 4 Q SHIFT E OUTPUTS LATCH 5 REGISTER Q F 6 Q G 7 Q H SHIFT 11 CLOCK SERIAL 10 9 RESET SQ DATA H OUTPUT LATCH 12 CLOCK V = PIN 16 CC 13 OUTPUT GND = PIN 8 ENABLE www.onsemi.com 2