Product Information

MC10EP35DG

MC10EP35DG electronic component of ON Semiconductor

Datasheet
Flip Flop JK-Master-Slave Type Pos-Edge 1-Element 8-Pin SOIC N Rail

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

98: USD 8.685 ea
Line Total: USD 851.13

0 - Global Stock
MOQ: 98  Multiples: 98
Pack Size: 98
Availability Price Quantity
0 - Global Stock


Ships to you between Mon. 06 May to Fri. 10 May

MOQ : 98
Multiples : 98

Stock Image

MC10EP35DG
ON Semiconductor

98 : USD 8.685

0 - Global Stock


Ships to you between Mon. 06 May to Fri. 10 May

MOQ : 98
Multiples : 98

Stock Image

MC10EP35DG
ON Semiconductor

98 : USD 9.4053
3822 : USD 9.2172
7644 : USD 9.2172
11466 : USD 9.2172

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Family
Logic Type
Polarity
Input Type
Output Type
Propagation Delay Time
High Level Output Current
Low Level Output Current
Supply Voltage - Min
Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Series
Brand
Number Of Input Lines
Number Of Output Lines
Packagingoptionsscrubbed
Factory Pack Quantity :
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MC100EP35 3.3 V / 5 VECL JK FlipFlop Description The MC100EP35 is a higher speed/low voltage version of the EL35 JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the www.onsemi.com outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. The 100 Series contains temperature compensation. 8 8 Features 1 1 410 ps Propagation Delay SOIC8 NB TSSOP8 Maximum Frequency > 3 GHz Typical D SUFFIX DT SUFFIX CASE CASE PECL Mode Operating Range: 75107 948R02 V = 3.0 V to 5.5 V with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 3.0 V to 5.5 V CC EE MARKING DIAGRAMS* Open Input Default State 8 8 Q Output Will Default LOW with Inputs Open or at V EE KEP35 KP35 These Devices are Pb-Free, Halogen Free and are RoHS Compliant ALYW ALYW 1 1 K = MC100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information on page 6 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: October, 2017 Rev. 8 MC10EP35/DMC100EP35 Table 1. PIN DESCRIPTION PIN FUNCTION J 1 8 V J CC CLK* ECL Clock Inputs J*, K* ECL Signal Inputs RESET* ECL Asynchronous Reset K 2 7 Q K Q, Q ECL Data Outputs Flip Flop V Positive Supply CC V Negative Supply EE CLK 3 6 Q * Pins will default LOW when left open. R Table 2. TRUTH TABLE J K RESET CLK Qn+1 RESET45 V EE L L L Z Qn L H L Z L H L L Z H H H L Z Qn Figure 1. 8-Lead Pinout (Top View) and Logic Diagram X X H X L Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 NB Level 1 TSSOP8 Level 3 Flammability Rating UL94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 77 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

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