MC100EPT622FAG

MC100EPT622 3.3VLVTTL/LVCMOS to LVPECL Translator Description The MC100EPT622 is a 10Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V 24 23 22 21 20 19 18 17 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 1234567 8 MC100EPT622 ENPECL V D4 D3 D2 V D1 D0 V CCO EE CCO ENTTL D0 Q0 V D5 CCO D1 Q1 D6 Q0 D7 Q1 D2 Q2 D8 Q2 MC100EPT622 V D3 D9 CCO Q3 ENTTL Q3 LVCMOS/TTL D4 Q4 ENPECL Q4 LVPECL V V CCO EE D5 Q5 D6 V Q9 Q8 Q7 V Q6 Q5 V CCO CC CCO Q6 Warning: All V V and V pins must be externally con- CC, CCO, EE nected to Power Supply to guarantee proper operation. D7 Figure 1. 32 Lead LQFP Pinout (Top View) Exposed Pad Q7 (EP) V D4 D3 D2 V D1 D0 V CCO EE CCO 32 31 30 29 28 27 26 25 D8 Q8 D5 1 24 V CCO D6 2 23 Q0 D9 Q9 D7 3 22 Q1 D8 Figure 2. Logic Symbol 4 21 Q2 5 20 D9 V CCO ENTTL 6 19 Q3 7 ENPECL 18 Q4 8 17 V EE V CCO 9 10 11 12 13 14 15 16 V Q9 Q8 Q7 V Q6 Q5 V CCO CC CCO Figure 3. 32Lead QFN Pinout (Top View) Table 1. PIN DESCRIPTION Pin Function D0:9 Data Input (TTL) Q0:9 Data Outputs (PECL) ENTTL Enable Control (TTL) ENPECL Enable Control (PECL) V , V Positive Supply CC CCO V Ground EE EP The exposed pad (EP) on the QFN32 package bottom is thermally connected to the die for improved heat transfer out of the package. THe exposed pad must be attached to a heat sinking conduit. The pad is electrically connected to V . EE