Product Information

MC100EP51DR2G

MC100EP51DR2G electronic component of ON Semiconductor

Datasheet
Flip Flop D-Master-Slave Type Pos-Edge/Neg-Edge 1-Element 8-Pin SOIC N T/R

Manufacturer: ON Semiconductor
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

2500: USD 4.3694 ea
Line Total: USD 10923.5

0 - Global Stock
MOQ: 2500  Multiples: 2500
Pack Size: 2500
Availability Price Quantity
0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 2500
Multiples : 2500

Stock Image

MC100EP51DR2G
ON Semiconductor

2500 : USD 15.0525
5000 : USD 14.9738
10000 : USD 14.8938
15000 : USD 14.8125
20000 : USD 14.7312
25000 : USD 14.6488
30000 : USD 14.5662
50000 : USD 14.4825
100000 : USD 14.3975

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 61
Multiples : 1

Stock Image

MC100EP51DR2G
ON Semiconductor

61 : USD 5.2314

0 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 2500
Multiples : 2500

Stock Image

MC100EP51DR2G
ON Semiconductor

2500 : USD 10.925

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 2500
Multiples : 2500

Stock Image

MC100EP51DR2G
ON Semiconductor

2500 : USD 4.7406

0 - Global Stock


Ships to you between Fri. 03 May to Thu. 09 May

MOQ : 2500
Multiples : 2500

Stock Image

MC100EP51DR2G
ON Semiconductor

2500 : USD 4.3694

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Number of Circuits
Logic Family
Logic Type
Polarity
Input Type
Output Type
Propagation Delay Time
High Level Output Current
Low Level Output Current
Supply Voltage - Min
Supply Voltage - Max
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
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Packaging
Series
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Number Of Input Lines
Number Of Output Lines
Factory Pack Quantity :
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MC10EP51, MC100EP51 3.3V / 5VECL D Flip-Flop with Reset and Differential Clock Description MC10EP51, MC100EP51 Table 1. PIN DESCRIPTION PIN FUNCTION RESET 1 8 V CC CLK*, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset R D* ECL Data Input D 2 7 Q D Q, Q ECL Data Outputs V Positive Supply CC Flip-Flop V Negative Supply EE CLK 3 6 Q EP (DFN8 only) Thermal exposed pad must be connected to a suf- ficient thermal conduit. Electric- ally connect to the most negative supply (GND) or leave uncon- nected, floating open. CLK45 V EE * Pins will default LOW when left open. Table 2. TRUTH TABLE Figure 1. 8Lead Pinout (Top View) and Logic Diagram D R CLK Q L L Z L H L Z H X H X L Z = LOW to HIGH Transition Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 2 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb Pkg PbFree Pkg SOIC8 Level 1 Level 1 TSSOP8 Level 1 Level 3 DFN8 Level 1 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 165 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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