EVBUM2284/D KLI-4104 Imager Board User s Manual Description The KLI4104 Imager Evaluation Board, referred to in this document as the Imager Board, is designed to be used www.onsemi.com as part of a twoboard set, used in conjunction with a Timing Generator Board. ON Semiconductor offers an Imager EVAL BOARD USERS MANUAL Board / Timing Generator Board package that has been designed and configured to operate with the KLI4104 Image Sensors. 30MHz pixel clocking rate and nominal operating The Timing Generator Board generates the timing signals conditions. (See the KLI4104 performance specifications necessary to operate the CCD, and provides the power for details). required by the Imager Board. The timing signals, in LVDS For testing and characterization purposes, the KLI4104 format, and the power, are provided to the Imager Board via Imager board provides the ability to adjust many of the CCD the interface connector (J5). In addition, the Timing bias voltages and CCD clock level voltages by adjusting Generator Board performs the processing and digitization of potentiometers on the board. The Imager Board provides the the analog video output of the Imager Board. means to modify other device operating parameters (e.g., The KLI4104 Imager Board has been designed to CCD Reset clock pulse width, Input Diode clock pulse operate the KLI4104 with the specified performance at width) by populating components differently on the board. INPUT REQUIREMENTS Table 1. POWER REQUIREMENTS Power Supplies Minimum Typical Maximum Units Comments 4.9 5.0 5.1 V +5 V MTR Supply 1.3 A 5 V MTR Supply 5.1 5.0 4.9 V 0.2 A VPLUS Supply 18 20 21 V 1.8 A Total Power Dissipation 42 W Air cooling recommended Table 2. SIGNAL LEVEL REQUIREMENTS Input Signals (LVDS) V V V Units Comments min threshold max H1A () 0 0.1 2.4 V H1 clock H1B () 0 0.1 2.4 V ID clock H2A () 0 0.1 2.4 V H2 clock H2B () 0 0.1 2.4 V (not used) FDG 0 0.1 2.4 V LOGR clock R () 0 0.1 2.4 V Reset clock V1 () 0 0.1 2.4 V TG1 clock V2 () 0 0.1 2.4 V TG2 clock V2B () 0 0.1 2.4 V LOGB clock V3RD () 0 0.1 2.4 V LOGG clock VES () 0 0.1 2.4 V LOGL clock Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: October, 2014 Rev. 2 EVBUM2284/DEVBUM2284/D KLI4104 IMAGER BOARD ARCHITECTURE OVERVIEW CCD TGCLK Drivers The following sections describe the functional blocks of The Transfer Gate clock (TGCLK) drivers consist of the KLI4104 Imager Board refer to Figure 1 and the MOSFET driver ICs. These drivers are designed to schematics. translate the TTLlevel clock signals to the voltage levels Power Filtering and Regulation required by the CCD. The high voltage levels of the TG Power is supplied to the Imager Board via the J1 interface clocks are set by potentiometers buffered by operational connector. The power supplies are de coupled and filtered amplifiers. with ferrite beads and capacitors to suppress noise. Voltage regulators are used to create the +15 V supply from the CCD LOG Drivers The Exposure Control (LOG) clocks are independently VPLUS supply. controlled linerate clocks, driven by a quad highcurrent NOTE: Because of the large capacitive load of the CCD pin driver. The LOG HIGH voltage level is set by a resistor horizontal clocks, the VPLUS supply will divider circuit, and is buffered by an operational amplifier. typically draw 1.8 A of current and heat sinking is installed under the voltage regulators VR1 and CCD Bias Voltages VR2. In addition, it is recommended that a The CCD bias voltages (TG1L, IG, OG, LS, RD) are set cooling fan be placed to the side of the board to by potentiometers, buffered by operational amplifiers. The create air flow over the heat sinks. This will bias voltages are decoupled at the CCD pin. prevent the CCD image sensor from exceeding its recommended operating temperature. CCD Image Sensor This evaluation board supports the KLI4104 Interline LVDS Receivers / TTL Buffers Image Sensor. LVDS timing signals are input to the Imager Board via the J5 board interface connector. These signals are shifted to EmitterFollower TTL levels before being sent to the CCD clock drivers. The VOUT CCD signals are buffered using bipolar junction transistors in the emitterfollower configuration. CCD PixelRate Clock Drivers (H1, H2 & Reset Clocks) These circuits also provide the necessary 5 mA current sink The pixel rate CCD clock drivers utilize two fast for the CCD output circuits. switching transistors that are designed to translate TTLlevel input clock signals to the voltage levels required Line Drivers by the CCD. The high level of the CCD clocks is set by The buffered VOUT CCD signals are ACcoupled and potentiometers buffered by operational amplifiers. driven from the Imager Board by operational amplifiers in Highcurrent pin drivers are used to drive the CCD a noninverting configuration. The operational amplifiers Horizontal clock gates. In order to effectively drive the are configured to have a gain of 1.125, to compensate for the capacitance of the Chroma Horizontal clock gates on the high amplitude video output, and to correctly drive 75 KLI4104, multiple pin drivers are configured in parallel. video coaxial cabling from the SMB connectors. H1L CCD Timing Adjustment Potentiometers Optional DAC Input Connector (P1) Minor timing adjustments can be made to the H1L CCD The P1 connector is provided for ON Semiconductor test right and left clock positions using the delay adjust purposes, and is not populated. potentiometers R180 and R181. Each potentiometer, along with a capacitor, forms an RC network that acts to delay the position of the H1L clock with respect to the H1A clock. Reset Clock & ID Clock OneShots The pulse widths of the RESET CCD and ID CCD clocks are set by programmable OneShots. Each OneShot can be configured to provide a clock signal with a pulse width from 5 ns to 15 ns.