74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs May 2007 74VHCT374A tm Octal D-Type Flip-Flop with 3-STATE Outputs Features General Description High speed: f = 140MHz (Typ.) at T = 25C The VHCT374A is an advanced high speed CMOS octal MAX A flip-flop with 3-STATE output fabricated with silicon gate High noise immunity: V = 2.0V, V = 0.8V IH IL CMOS technology. It achieves the high speed operation Power down protection is provided on all inputs and similar to equivalent Bipolar Schottky TTL while main- outputs taining the CMOS low power dissipation. This 8-bit Low power dissipation: I = 4A (Max.) T = 25C CC A D-type flip-flop is controlled by a clock input (CP) and an Pin and function compatible with 74HCT374 output enable input (OE ). When the OE input is HIGH, the eight outputs are in a high impedance state. Protection circuits ensure that 0V to 7V can be applied to (1) the input and output pins without regard to the supply voltage. This device can be used to interface 3V to 5V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mis- matched supply and input voltages. Note: 1. Outputs in OFF-State. Ordering Information Package Order Number Number Package Description 74VHCT374AM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74VHCT374ASJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHCT374AMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter X to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Description Pin Names Description D D Data Inputs 0 7 CP Clock Pulse Input 3-STATE Output Enable Input 3-STATE OE O O Outputs 0 7 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT374A Rev. 1.374VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs Logic Symbol Functional Description IEEE/IEC The VHCT374A consists of eight edge-triggered flip- flops with individual D-type inputs and 3-STATE true out- puts. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the con- tents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high imped- ance state. Operation of the OE input does not affect the state of the flip-flops. Truth Table Inputs Outputs D CP OE O n n H L H L L L X X H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHCT374A Rev. 1.3 2