Product Information

XC7WH126GD

XC7WH126GD electronic component of NXP

Datasheet
IC, DUAL, BUFF/DRIVER TRI-ST, XSON8U

Manufacturer: NXP
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.0699 ea
Line Total: USD 0.07

0 - Global Stock
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 10 May to Thu. 16 May

MOQ : 1
Multiples : 1
1 : USD 0.0699

     
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Product Category
Logic Device Type
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Supply Voltage Min
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Packaging
Msl
Svhc
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XC7WH126 Dual buffer/line driver 3-state Rev. 2 8 May 2013 Product data sheet 1. General description The XC7WH126 is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A LOW at nOE causes the output to assume a high-impedance OFF-state. 2. Features and benefits Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays Multiple package options ESD protection: HBM JESD22-A114E: exceeds 2000 V MM JESD22-A115-A: exceeds 200 V CDM JESD22-C101C: exceeds 1000 V Specified from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version XC7WH126DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package 8 leads SOT505-2 body width 3 mm lead length 0.5 mm XC7WH126DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package 8 SOT765-1 leads body width 2.3 mm XC7WH126GD 40 C to +125 C XSON8 plastic extremely thin small outline package no SOT996-2 leads 8 terminals body 3 2 0.5 mmXC7WH126 NXP Semiconductors Dual buffer/line driver 3-state 4. Marking Table 2. Marking codes 1 Type number Marking XC7WH126DP f26 XC7WH126DC f26 XC7WH126GD f26 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1Y 1A 2 2 6 6 1 1OE 1 1 EN1 nA nY 2Y 2A 5 5 3 3 2OE 7 7 nOE mna946 mna947 mna234 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one buffer) 6. Pinning information 6.1 Pinning XC7WH126 1OE 1 8 V CC 1A 2 7 2OE XC7WH126 2Y 3 6 1Y 1 8 1OE V CC 2 7 1A 2OE GND 4 5 2A 3 6 2Y 1Y 4 5 GND 2A 001aak068 001aak067 Transparent top view Fig 4. Pin configuration SOT505-2 (TSSOP8) and Fig 5. Pin configuration SOT996-2 (XSON8) SOT765-1 (VSSOP8) XC7WH126 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 2 8 May 2013 2 of 14

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