T4240NSN7PQB

Document Number T4240 NXP Semiconductors Rev. 1, 05/2016 Data Sheet: Technical Data T4240 QorIQ T4240 Data Sheet Features 32 SerDes lanes at up to 10 Gb/s 12 e6500 cores built on Power Architecture Ethernet interfaces technology and arranged as clusters of four e6500 Up to four 10 Gbps Ethernet MACs cores sharing a 2 MB L2 cache Up to sixteen 1 Gbps Ethernet MACs Combinations of 1 Gbps and 10 Gbps Ethernet 1.5 MB CoreNet platform cache (CPC) MACs Hierarchical interconnect fabric IEEE Std 1588 support CoreNet fabric supporting coherent and non- High-speed peripheral interfaces coherent transactions with prioritization and Four PCI Express 2.0/3.0 controllers running at up bandwidth allocation amongst CoreNet end-points to 8 GT/s with one controllers supporting end-point, 1.6 Tbps coherent read bandwidth single-root I/O virtualization (SR-IOV) Three 64-bit DDR3 SDRAM memory controllers Two Serial RapidIO 2.0 controllers running at up to DDR3 and DDR3L with ECC and interleaving 5 Gbaud support Interlaken look-aside interface for TCAM connection Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: Additional peripheral interfaces Packet parsing, classification, and distribution Two Serial ATA (SATA 2.0) controllers (Frame Manager 1.1) Two high-speed USB 2.0 controllers with integrated Queue management for scheduling, packet PHY sequencing, and congestion management (Queue Enhanced secure digital host controller (SD/MMC/ Manager 1.1) eMMC) Hardware buffer management for buffer allocation Enhanced Serial peripheral interface (eSPI) and de-allocation (Buffer Manager 1.1) Four I2C controllers Cryptography Acceleration (SEC 5.0) Four 2-pin UARTs or two 4-pin DUARTs RegEx Pattern Matching Acceleration (PME 2.0) Integrated flash controller supporting NAND and Decompression/Compression Acceleration (DCE NOR flash 1.0) Three 8-channel DMA engines DPAA chip-to-chip interconnect via RapidIO Message Manager (RMan 1.0) 1932 FC-PBGA package, 45 mm x 45 mm, 1mm pitch NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. 20142016 NXP B.V.Table of Contents 1 Overview.............................................................................................. 3 3.16 JTAG controller.........................................................................124 2 Pin assignments.................................................................................... 3 3.17 I2C interface.............................................................................. 127 2.1 1932 ball layout diagrams......................................................... 4 3.18 GPIO interface...........................................................................130 2.2 Pinout list...................................................................................10 3.19 High-speed serial interfaces (HSSI).......................................... 132 3 Electrical characteristics.......................................................................73 4 Hardware design considerations...........................................................188 3.1 Overall DC electrical characteristics.........................................73 4.1 System clocking........................................................................ 188 3.2 Power sequencing......................................................................80 4.2 Power supply design..................................................................204 3.3 Power-down requirements.........................................................82 4.3 Decoupling recommendations...................................................213 3.4 Power characteristics.................................................................83 4.4 SerDes block power supply decoupling recommendations.......213 3.5 Power-on ramp rate................................................................... 90 4.5 Connection recommendations................................................... 214 3.6 Input clocks............................................................................... 91 4.6 Thermal......................................................................................225 3.7 RESET initialization..................................................................96 4.7 Recommended thermal model...................................................226 3.8 DDR3 and DDR3L SDRAM controller.................................... 97 4.8 Thermal management information............................................ 226 3.9 eSPI interface.............................................................................103 5 Package information.............................................................................229 3.10 DUART interface...................................................................... 106 5.1 Package parameters for the FC-PBGA......................................229 3.11 Ethernet interface, Ethernet management interface 1 and 2, 5.2 Mechanical dimensions of the FC-PBGA................................. 229 IEEE Std 1588........................................................................... 107 6 Security fuse processor.........................................................................231 3.12 USB interface............................................................................ 116 7 Ordering information............................................................................231 3.13 Integrated flash controller..........................................................118 7.1 Part numbering nomenclature....................................................231 3.14 Enhanced secure digital host controller (eSDHC).....................121 7.2 Orderable part numbers addressed by this document................232 3.15 Multicore programmable interrupt controller (MPIC).............. 123 8 Revision history....................................................................................234 QorIQ T4240 Data Sheet, Rev. 1, 05/2016 2 NXP Semiconductors