NXP Semiconductors KM35P144M75SF0 Data Sheet: Technical Data Rev. 2, March 2020 Kinetis KM35 Sub-Family Data MKM35Z256VLL7 MKM35Z256VLQ7 Sheet MKM35Z512VLL7 MKM35Z512VLQ7 Enabling high accuracy, secure 1-, 2- and 3-phase electricity metering solutions through a powerful analog front end (AFE), auto-compensated iRTC with hardware tamper detection, segment LCD controller, rich security protection and multiple low power features in a 32-bit Arm Cortex -M0+ MCU. This product offers: Enabling single-chip 1-, 2- and 3-phase metering designs AFE, Security and HMI. Single crystal implementation Single point of calibration during manufacture Highest accuracy metrology with regional feature support 100 LQFP 144 LQFP Multiple ADCs with PGA 14 mm 14 mm Pitch 20 mm 20 mm Pitch 0.5 mm 0.5 mm Supports neutral disconnect use case Compliance with WELMEC/OIML recommendations Memory and peripheral protection Hardware tamper detect with time stamping Low-power RTC, battery backup with tamper memory Core Memories Arm Cortex -M0+ core up to 75 MHz Up to 512 KB program flash memory Metering specific Memory Mapped Arithmetic Unit Up to 64 KB SRAM (MMAU) Operating Characteristics Clocks Voltage range: 1.71 to 3.6 V (without AFE) 75 MHz high-accuracy internal reference clock Voltage range: 2.7 to 3.6 V (with AFE) 32 kHz, and 4 MHz internal reference clock Temperature range (ambient): 40 to 105 C 1 kHz LPO clock Low power features 32.768 kHz crystal oscillator in iRTC power domain 13 power modes to provide power optimization 1 MHz to 32 MHz crystal oscillator based on application requirements FLL and PLL 8.82 mA 75 MHz run current System peripherals Less than 220 A very low power run current Memory Protection Unit (MPU) 6.05 A very low power stop current 4-channel DMA controller Down to 261 nA deep sleep current Watchdog and EWM V domain current < 1 A with iRTC operational BAT Low-leakage Wakeup Unit (LLWU) Low-power boot with less than 2.33 mA peak SWD debug interface and Micro Trace Buffer (MTB) current Bit Manipulation Engine (BME) Communication interfaces Inter-peripheral Crossbar Switch (XBAR) 16-bit SPI modules Analog Modules Low-power UART module 4 AFE channels (4 24-bit ADCs with PGA) UART module complying with ISO7816-3 16-channel 16-bit SAR ADC with 4 result registers Basic UART module 2 High-speed analog comparator containing a 6-bit DAC I C with SMBus and programmable reference input Internal 1.2 V reference voltage 1015 ppm/ NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.Timers Security and integrity modules Quad Timer (QTMR) Memory Mapped Cryptographic Acceleration Unit Periodic Interrupt Timer (PIT) (MMCAU) for AES encryption Low Power Timer (LPTMR) Random Number Generator (RNGA), complying Programmable Delay Block (PDB) with NIST: SP800-90 Independent Real Time Clock (iRTC) Programmable Cyclic Redundancy Check (PCRC) 80-bit unique identification number per chip Human-machine interface Up to 460 (856, 658) segment LCD controller operating in all low-power modes General purpose input/output (GPIO) The following figure shows the functional modules in the chip. Accessed by Micro Transfer Buffer (MTB) for trace TCU MMAU MMCAU Serial Serial SRAM S1 Wire Wire (64 KB) MTB Debug Debug MPU (part of PPB) M0 Flash Flash S0 Controller (512 KB) Interrupt IOPORT from NVIC (part of PPB) Port P0 Modules Port P1 AIPS eGPIO GPIO Arm Cortex S2 BME (AHB to IPS) (dual port) Pins M0+ Core Multiple DMA DMA 4-ch Requests M2 MUX DMA from IPS Bus Modules Single Ended SAR Channels ADC AHB PIT PCRC I2C Digital Crossbar XBAR PDB RNGA x2 x2 I/Os Switch Comparator CMP Inputs x3 WDOG LCD AFE SIM SMC QTMR SLCD EWM Pins Modulator Clock Dec UART MCG Digital CLK LPTMR x4, LLWU PMC VREF Filter PLL GEN I/Os x2 x4 LPUART IRC 4 MHz OSC OSC RTC SD ADC x4 SPI Digital IRTC IRC MHz 32k POR + PGA x4 I/Os x3 FLL 32 kHz Refer Clocking TAMPER Core, System and SD ADC Channels Chapter for more x4 Analog Front End Flash Clocks detailed diagram Fine Compensation Clock on MCG Modules in Modules in Modules in VDDA Domain VBAT Domain VDD Domain Figure 1. Functional block diagram 2 Kinetis KM35 Sub-Family Data Sheet, Rev. 2, March 2020 NXP Semiconductors EXTAL XTAL EXTAL32 XTAL32