MCF5327CVM240

Document Number: MCF5251 Freescale Semiconductor Rev. 3, 04/2008 Data Sheet: Technical Data MCF5251 Package Information MAPBGA225 MCF5251 ColdFire Ordering Information: See Table 1 on page 2 Microprocessor Data Sheet 1 Introduction 1 1 Introduction 1.1 Orderable Part Numbers 2 1.2 Block Diagram 3 This document provides an overview of the MCF5251 2 Functional Description . 4 ColdFire processor and general descriptions of the 2.1 Version 2 ColdFire Core . 4 MCF5251 features and modules. Also provided are 2.2 Module Inventory 4 electrical specifications, pin assignments, and package 3 Signal Description 6 4 Electrical Specifications . 11 diagrams for MCF5251 ColdFire processor. For 4.1 SDRAM Bus Timing . 16 functional characteristics, refer to the MCF5251 4.2 SPDIF Timing 17 Reference Manual (MCF5251RM). 4.3 Serial Audio Interface Timing 17 4.4 DDATA/PST/PSTCLK Debug Interface 17 The MCF5251 is a system controller/decoder for 4.5 BDM and JTAG Timing 18 compressed audio music players addressing both 5 Package Information and Pinout 19 portable and automotive solutions supporting CD, HDD 5.1 Pin Assignment 19 5.2 Package Drawing . 25 and USB based systems. The 32-bit ColdFire core with 6 Product Documentation . 33 enhanced multiply and accumulate (eMAC) unit 6.1 Revision History 33 provides optimum performance and code density for the combination of control code and signal processing required for compressed audio decode, file management, and system control. The MCF5251 is a general purpose system controller with over 125 Dhrystone 2.1 MIPS 140 MHz performance. The integrated peripherals and EMAC allow the MCF5251 to replace both the microcontroller Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2008. All rights reserved. Introduction and the DSP in certain applications. Most peripheral pins can also be remapped as general purpose I/O pins. Low power features include flexible PLL (with power-down mode) with dynamic clock switching, a hardwired CD ROM decoder, advanced 0.13 m CMOS process technology, 1.2 V core power supply, and on-chip 128K-byte SRAM. MP3 decode requires less than 20 MHz CPU bandwidth and runs from on-chip SRAM. For additional information regarding software drivers and applications, refer to