HEF4557BP,652

HEF4557B 1-to-64 bit variable length shift register Rev. 6 18 November 2011 Product data sheet 1. General description The HEF4557B is a static clocked serial shift register whose length may be programmed to be any number of bits between 1 and 64. The number of bits selected is equal to the sum of the subscripts of the enabled length control inputs (L1, L2, L4, L8, L16, and L32) plus one. Serial data may be selected from the DA or DB data inputs with the A/B select input. This feature is useful for recirculation purposes. Information on DA or DB is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP0 while CP1 is LOW or on the HIGH to LOW transition of CP1 while CP0 is HIGH. A HIGH on master reset (MR) resets the register and forces Q to LOW and Q to HIGH, independent of the other inputs. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +85 C Type number Package Name Description Version HEF4557BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4557BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1HEF4557B NXP Semiconductors 1-to-64 bit variable length shift register 4. Functional diagram HEF4557B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 18 November 2011 2 of 17 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x L32 L16 L8 A/B DA DB FF1 FF32 FF33 FF48 FF49 FF56 D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CD CD CD CD CD CD CP1 CP0 L4 L2 L1 MR FF57 FF60 FF61 FF62 FF63 FF64 D Q D Q D Q D Q Q D Q D Q CP CP CP CP CP CP Q CD CD CD CD CD CD 001aae782 Fig 1. Logic diagram