Freescale Semiconductor Document Number: BSC9131 Data Sheet: Technical Data Rev. 0, 03/2014 BSC9131 BSC9131 QorIQ Qonverge Multicore Baseband FC-PBGA520 21 mm x 21 mm Processor The following list provides an overview of the feature set: TCP/IP acceleration, quality of service, and classification capabilities High-performance 32-bit e500 core built on Power IEEE Std 1588 support Architecture technology: eTSEC1 supports RGMII and RMII interfaces 36-bit physical addressing eTSEC2 supports an RGMII interface Double-precision floating-point support High-speed USB controller (USB 2.0) 32-Kbyte L1 instruction cache and 32-Kbyte L1 data Host and device support cache Enhanced host controller interface (EHCI) Enhanced hardware and software debug support ULPI interface 800 MHz/1 GHz clock frequency Enhanced secure digital (SD/MMC) host controller 256-Kbyte L2 cache with ECC also configurable as (eSDHC) SRAM and stashing memory Integrated Flash controller (IFC), supporting NAND, One SC3850 core subsystem, which connects to the NOR, and general ASIC following: TDM with one TDM port 32 Kbyte 8-way level 1 data/instruction cache Antenna interface controller (AIC), supporting three (L1 Dcache/ICache) industry standard JESD/three custom parallel RF interfaces 512 Kbyte 8-way level 2 unified instruction/data cache (two dual and one single port) and three MAXIM s (L2 cache/M2 memory) MaxPHY serial interfaces Memory management unit (MMU) Universal Subscriber Identity Module (USIM) interface Enhanced programmable interrupt controller (EPIC) Facilitates communication to SIM cards or Eurochip Debug and profiling unit (DPU) pre-paid phone cards Two 32-bit quad timers Four enhanced serial peripheral interfaces (eSPI) Multi Accelerator Platform Engine for Femto Base Station Programmable interrupt controller (PIC) compliant with Baseband Processing (MAPLE-B2F) OpenPIC standard Supports variable sizes in Fourier Transforms, One four-channel DMA controller Convolution, Filtering, Turbo, Viterbi, Chiprate 2 Two I C interfaces Consists of accelerators for UMTS chip rate processing, Two dual UART (DUART) interfaces LTE UP/DL channel processing, Matrix Inversion Two pulse-width modulator (PWM) interfaces operations, and CRC algorithms 96 general-purpose I/O signals DDR3/DDR3L SDRAM memory controller supports Eight 32-bit timers 32-bit without ECC and 16-bit with ECC Operating temperature (Ta - T ) range: 0105 C Integrated security engine (ULE CAAM) j Protocol support includes DES, AES, RNG, CRC, MDE, PKE, SHA, and MD5 Secure boot capability Two enhanced three-speed Ethernet controllers (eTSECs) 10/100/1000 Mbps support 2014 Freescale Semiconductor, Inc. All rights reserved.Table of Contents 1 Pin Assignments 3 2.20 Radio Frequency (RF) Interface 101 1.1 Ball Layout Diagrams .4 2.21 Universal Subscriber Identity Module (USIM) 108 1.2 Pinout Assignments 9 2.22 Timers and Timers 32b AC Timing Specifications 112 2 Electrical Characteristics 48 3 Hardware Design Considerations 113 2.1 Overall DC Electrical Characteristics 48 3.1 Power Architecture System Clocking . 113 2.2 Power Sequencing 52 3.2 DSP System Clocking 116 2.3 Power-Down Requirements .54 3.3 Supply Power Default Setting 117 2.4 RESET Initialization .54 3.4 PLL Power Supply Design . 117 2.5 Power-on Ramp Rate 54 3.5 Decoupling Recommendations . 118 2.6 Power Characteristics 55 3.6 Pull-Up and Pull-Down Resistor Requirements . 119 2.7 Input Clocks .56 3.7 Output Buffer DC Impedance 119 2.8 DDR3 and DDR3L SDRAM Controller .61 3.8 Configuration Pin Muxing . 120 2.9 eSPI .68 3.9 JTAG Configuration Signals 120 2.10 DUART .70 3.10 Thermal . 122 2.11 Ethernet: Enhanced Three-Speed Ethernet (eTSEC) .71 3.11 Security Fuse Processor 123 2.12 USB 79 4 Package Information 123 2.13 Integrated Flash Controller (IFC) .82 4.1 Package Parameters . 123 2.14 Enhanced Secure Digital Host Controller (eSDHC) .86 4.2 Mechanical Dimensions of the FC-PBGA . 125 2.15 Programmable Interrupt Controller (PIC) Specifications88 5 Ordering Information 126 2.16 JTAG .91 5.1 Part Marking . 126 2 2.17 I C .93 6 Product Documentation 126 2.18 GPIO .95 7 Revision History . 127 2.19 TDM .97 BSC9131 QorIQ Qonverge Baseband Processor Data Sheet, Rev. 0 2 Freescale Semiconductor