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74LV273D,118

74LV273D,118 electronic component of NXP

Datasheet
IC D-TYPE POS TRG SNGL 20SOIC
Manufacturer: NXP
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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Additional Infomation About Product

INTEGRATED CIRCUITS 74LV273 Octal D-type flip-flop with reset positive-edge trigger Product specification 1998 May 29 Supersedes data of 1997 Apr 07 IC24 Data Handbook Philips Semiconductors Product specification 74LV273 Octal D-type flip-flop with reset positive edge-trigger FEATURES DESCRIPTION The 74LV273 is a low-voltage Si-gate CMOS device and is pin and Wide operating voltage: 1.0 to 5.5V function compatible with the 74HC/HCT273. Optimized for Low Voltage applications: 1.0 to 3.6V The 74LV273 has eight edge-triggered , D-type flip-flops with Accepts TTL input levels between V = 2.7V and V = 3.6V individual D inputs and Q outputs. The common clock (CP) and CC CC master reset (MR) inputs load and reset (clear) all flip-flops Typical V (output ground bounce) 0.8V V = 3.3V, OLP CC simultaneously. The state of each D input, one set-up time before T = 25C amb the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. Typical V (output V undershoot) 2V V = 3.3V, OHV OH CC T = 25C amb All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. Ideal buffer for MOS microprocessor or memory The device is useful for applications where the true output only is Common clock and master reset required and the clock and master reset are common to all storage Output capability: standard elements. I category: MSI CC QUICK REFERENCE DATA GND = 0V T = 25C t =t 2.5 ns amb r f SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay 12 C = 15pF t /t CP to Q L ns n PHL PLH 13 V = 3.3V MR to Q CC n f Maximum clock frequency 110 MHz max C Input capacitance 3.5 pF I C Power dissipation capacitance per flip-flop Notes 1 and 2 20 pF PD NOTES: 1. C is used to determine the dynamic power dissipation (P in W) PD D 2 2 P = C V x f (C V f ) where: D PD CC i L CC o f = input frequency in MHz C = output load capacitance in pF i L f = output frequency in MHz V = supply voltage in V o CC 2 (C V f ) = sum of the outputs. L CC o 2. The condition is V = GND to V I CC ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. 20-Pin Plastic DIL 40C to +125C 74LV273 N 74LV273 N SOT146-1 20-Pin Plastic SO 40C to +125C 74LV273 D 74LV273 D SOT163-1 20-Pin Plastic SSOP Type II 40C to +125C 74LV273 DB 74LV273 DB SOT339-1 20-Pin Plastic TSSOP 40C to +125C 74LV273 PW 74LV273PW DH SOT360-1 2 1998 May 29 8531965 19466

HS Compliance

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits

NXP may also be referenced as

FR9
Freescale
FREESCALE SEMI
Freescale Semicon
FREESCALE SEMICONDUC
Freescale Semiconductor
Freescale Semiconductor - NXP
NXP
NXP Freescale
NXP (FREESCALE)
NXP / Freescale
NXP SEMI
NXP Semicon
NXP SEMICONDUCTOR
NXP Semiconductors
NXP USA Inc.
PH3
PHI

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