74HCT4511N

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4511 BCD to 7-segment latch/decoder/driver December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication BCD to 7-segment latch/decoder/driver 74HC/HCT4511 FEATURES ripple blanking input (BI), an active LOW lamp test input (LT), and seven active HIGH segment outputs (Q to Q ). a g Latch storage of BCD inputs When LE is LOW, the state of the segment outputs (Q to a Blanking input Q ) is determined by the data on D to D . g 1 4 Lamp test input When LE goes HIGH, the last data present on D to D are 1 4 Driving common cathode LED displays stored in the latches and the segment outputs remain stable. Guaranteed 10 mA drive capability per output When LT is LOW, all the segment outputs are HIGH Output capability: non-standard independent of all other input conditions. With LT HIGH, a I category: MSI CC LOW on BI forces all segment outputs LOW. The inputs LT and BI do not affect the latch circuit. GENERAL DESCRIPTION APPLICATIONS The 74HC/HCT4511 are high-speed Si-gate CMOS devices and are pin compatible with 4511 of the 4000B Driving LED displays series. They are specified in compliance with JEDEC Driving incandescent displays standard no. 7A. Driving fluorescent displays The 74HC/HCT4511 are BCD to 7-segment Driving LCD displays latch/decoder/drivers with four address inputs (D to D ), 1 4 Driving gas discharge displays an active LOW latch enable input (LE), an active LOW QUICK REFERENCE DATA GND = 0 V T =25C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF V =5 V PHL PLH L CC D to Q 24 24 ns n n LE to Q 23 24 ns n BI to Q 19 20 ns n LT to Q 12 13 ns n C input capacitance 3.5 3.5 pF I C power dissipation capacitance per latch notes 1 and 2 64 64 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC December 1990 2