74HC377N,652

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT377 Octal D-type flip-flop with data enable positive-edge trigger December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Octal D-type ip-op with data enable 74HC/HCT377 positive-edge trigger FEATURES GENERAL DESCRIPTION Ideal for addressable register applications The 74HC/HCT377 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL Data enable for address and data synchronization (LSTTL). They are specified in compliance with JEDEC applications standard no. 7A. Eight positive-edge triggered D-type flip-flops The 74HC/HCT377 have eight edge-triggered, D-type See 273 for master reset version flip-flops with individual D inputs and Q outputs. A common See 373 for transparent latch version clock (CP) input loads all flip-flops simultaneously when See 374 for 3-state version the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is Output capability: standard transferred to the corresponding output (Q ) of the flip-flop. n I category: MSI CC The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay CP to Q C = 15 pF V = 5 V 13 14 ns PHL PLH n L CC f maximum clock frequency 77 53 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per ip-op notes 1 and 2 20 20 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2