74AVCH4T245D

74AVCH4T245 4-bit dual supply translating transceiver with configurable voltage translation 3-state Rev. 5 17 December 2015 Product data sheet 1. General description The 74AVCH4T245 is a 4-bit, dual supply transceiver that enables bidirectional level translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It features two 2-bit input-output ports (nAn and nBn), a direction control input (nDIR), a output enable input (nOE) and dual supply pins (V and V ). Both V and CC(A) CC(B) CC(A) V can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable CC(B) for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nAn, nOE and nDIR are referenced to V and pins nBn are referenced to CC(A) V . A HIGH on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows CC(B) transmission from nBn to nAn. The output enable input (nOE) can be used to disable the outputs so the buses are effectively isolated. The device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at CC(A) CC(B) GND level, both nAn and nBn outputs are in the high-impedance OFF-state. The bus hold circuitry on the powered-up side always stays active. The 74AVCH4T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features and benefits Wide supply voltage range: V : 0.8 V to 3.6 V CC(A) V : 0.8 V to 3.6 V CC(B) Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation)74AVCH4T245 NXP Semiconductors 4-bit dual supply translating transceiver 3-state 200 Mbit/s ( 1.1 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 2.5 V translation) 200 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Bus hold on data inputs Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVCH4T245D 40 Cto+125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74AVCH4T245PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74AVCH4T245BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 74AVCH4T245GU 40 C to +125 C XQFN16 plastic, extremely thin quad flat package no leads SOT1161-1 16 terminals body 1.80 2.60 0.50 mm 4. Marking Table 2. Marking codes Type number Marking code 74AVCH4T245D 74AVCH4T245D 74AVCH4T245PW CH4T245 74AVCH4T245BQ H4T245 74AVCH4T245GU K4 74AVCH4T245 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 17 December 2015 2 of 29