74AUP1T97GS

74AUP1T97 Low-power configurable gate with voltage-level translator Rev. 5 17 September 2015 Product data sheet 1. General description The 74AUP1T97 provides low-power, low-voltage configurable logic gate functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to V or GND. CC This device ensures a very low static and dynamic power consumption across the entire V range from 2.3 V to 3.6 V. CC The 74AUP1T97 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V. This device is fully specified for partial power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire V range. CC 2. Features and benefits Wide supply voltage range from 2.3 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 1.5 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP1T97 NXP Semiconductors Low-power configurable gate with voltage-level translator 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1T97GW 40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP1T97GM 40 C to +125 C XSON6 plastic extremely thin small outline package SOT886 no leads 6 terminals body 1 1.45 0.5 mm 74AUP1T97GF 40 C to +125 C XSON6 plastic extremely thin small outline package SOT891 no leads 6 terminals body 1 1 0.5 mm 74AUP1T97GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1T97GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 74AUP1T97GX 40 C to +125 C X2SON6 plastic thermal extremely thin small outline package SOT1255 no leads 6 terminals body 1 0.8 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74AUP1T97GW 59 74AUP1T97GM 59 74AUP1T97GF 59 74AUP1T97GN 59 74AUP1T97GS 59 74AUP1T97GX 59 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram < % & DG D Fig 1. Logic symbol 74AUP1T97 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 5 17 September 2015 2 of 22