74ALVCH16244DL,118

74ALVC16244 74ALVCH16244 2.5 V / 3.3 V 16-bit buffer/line driver 3-state Rev. 6 22 July 2021 Product data sheet 1. General description The 74ALVC16244 74ALVCH16244 is a 16-bit buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. This device is fully specified for partial power down applications using I . The I circuitry disables the output, preventing the OFF OFF potentially damaging backflow current through the device when it is powered down. The 74ALVCH16244 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption MultiByte flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Overvoltage tolerant inputs to 5.5 V Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF All data inputs have bushold (74ALVCH16244 only) Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) Output drive capability 50 transmission lines at 85 C Current drive 24 mA at 3.0 V ESD protection: HBM JESD22-A114-A exceeds 2000 V MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC16244DGG -40 C to +85 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mm 74ALVCH16244DGGNexperia 74ALVC16244 74ALVCH16244 2.5 V / 3.3 V 16-bit buffer/line driver 3-state 4. Functional diagram 47 2 36 13 1A0 1Y0 3A0 3Y0 46 3 35 14 1A1 1Y1 3A1 3Y1 1 1OE EN1 48 2OE EN2 44 5 33 16 25 1A2 3A2 1Y2 3Y2 3OE EN3 24 4OE EN4 6 17 43 32 47 2 1A3 1Y3 3A3 3Y3 1A0 1 1 1Y0 46 3 1A1 1Y1 1 25 44 5 1OE 3OE 1A2 1Y2 43 6 1A3 1Y3 41 8 2A0 1 2 2Y0 40 9 41 8 30 19 2A1 2Y1 2A0 2Y0 4A0 4Y0 38 11 2A2 2Y2 37 12 2A3 2Y3 40 9 29 20 36 13 2A1 4A1 2Y1 4Y1 3A0 1 3 3Y0 35 14 3A1 3Y1 33 16 3A2 3Y2 38 11 27 22 17 2A2 4A2 32 2Y2 4Y2 3A3 3Y3 30 19 4A0 1 4 4Y0 29 20 37 12 26 23 4A1 4Y1 2A3 2Y3 4A3 4Y3 27 22 4A2 4Y2 26 23 48 24 4A3 4Y3 2OE 4OE mna996 001aae231 Fig. 1. Logic symbol Fig. 2. IEC logic symbol V CC data input to internal circuit mna705 Fig. 3. Bus hold circuit 74ALVC ALVCH16244 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 22 July 2021 2 / 13