Product Information

74ALVC74D,118

74ALVC74D,118 electronic component of Nexperia

Datasheet
Flip Flops 3.3V 2 D F-F S/RSET

Manufacturer: Nexperia
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

1: USD 0.7036 ea
Line Total: USD 0.7

4247 - Global Stock
Ships to you between
Thu. 09 May to Mon. 13 May
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
2473 - Global Stock


Ships to you between Thu. 09 May to Mon. 13 May

MOQ : 1
Multiples : 1

Stock Image

74ALVC74D,118
Nexperia

1 : USD 0.4669
10 : USD 0.3806
100 : USD 0.2863
500 : USD 0.2403
1000 : USD 0.1944
2500 : USD 0.1714
10000 : USD 0.1564
25000 : USD 0.1541
50000 : USD 0.1506

     
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RoHS - XON
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74ALVC74 Dual D-type flip-flop with set and reset positive-edge trigger Rev. 6 27 July 2021 Product data sheet 1. General description The 74ALVC74 is a dual positive edge triggered, D-type flip-flop. It has individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs that operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. 2. Features and benefits Wide supply voltage range from 1.65 V to 3.6 V Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B (2.7 to 3.6 V) 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 CNexperia 74ALVC74 Dual D-type flip-flop with set and reset positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC74D -40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74ALVC74PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74ALVC74BQ -40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mm 4. Functional diagram 4 5 S 4 10 3 C1 1SD 2SD 2 1D SD 6 2 1D 1Q 5 1 D Q R 12 2D 2Q 9 3 1CP CP FF 11 2CP 10 9 S 1Q 6 11 Q C2 2Q 8 RD 12 2D 8 1RD 2RD 13 R 1 13 aaa-008836 aaa-008837 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 74ALVC74 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 27 July 2021 2 / 16

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Nexperia
NEXPERIA USA INC
Nexperia USA Inc.

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