HEF4040BT,653

HEF4040B 12-stage binary ripple counter Rev. 10 7 December 2021 Product data sheet 1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications. 2. Features and benefits Wide supply voltage range from 3.0 V to 15.0 V CMOS low power dissipation High noise immunity Tolerant of slow clock rise and fall time Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Complies with JEDEC standard JESD 13-B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V Specified from -40 C to +85 C 3. Applications Frequency dividing circuits Time delay circuits Control counters 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version HEF4040BT -40 C to +85 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mmNexperia HEF4040B 12-stage binary ripple counter 5. Functional diagram 10 CP T 12-STAGE COUNTER 11 MR C D 9 7 6 5 3 2 4 13 12 14 15 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad589 Fig. 1. Functional diagram FF 1 FF 2 FF 12 Q Q Q CP T T T Q Q Q CD CD CD MR Q0 Q1 Q11 001aae615 Fig. 2. Logic diagram 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 CP input MR input Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 001aad587 Fig. 3. Timing diagram HEF4040B All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 10 7 December 2021 2 / 11